Main publications

2013

• M. Själander and P. Larsson-Edefors
  "FlexCore: Implementing an Exposed Datapath Processor"
  Proceedings of Int. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pp. 306-313,
  Samos, Greece, July 15-18 2013.

2012

• V. Saljooghi, A. Bardizbanyan, M. Själander, and P. Larsson-Edefors
  "Configurable RTL Model for Level-1 Caches"
  Proceedings of NORCHIP, Copenhagen, Denmark, Nov. 11-12 2012.
• M. W. Azhar, M. Själander, A. Hasan, A. Vijayashekar, T. Hoang-Thanh, K. K. Ansari, and P. Larsson-Edefors
  "Viterbi Accelerator for Embedded Processor Datapaths"
  Proceedings of IEEE Int. Conf. on Application-Specific Systems, Architectures and Processors (ASAP), pp. 133-140,
  Delft, the Netherlands, July 9-11 2012.

2011

• B. Hidaji, S. Alipour, K. P. Subramaniyan, and P. Larsson-Edefors
  "Application-Specific Energy Optimization of General-Purpose Datapath Interconnect"
  Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 301-306, Chennai, India, July 4-6 2011.
• T. T. Hoang, V. Saseendran, D. Siaudinis, and P. Larsson-Edefors
  "Power Gating Multiplier of Embedded Processor Datapath"
  Proceedings of IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME), pp. 41-44, Madonna Di Campiglio, Italy, July 3-7 2011.
• K. P. Subramaniyan, E. Ryman, M. Själander, T. T. Hoang, M. M. Islam, and P. Larsson-Edeforsxi
  "FlexDEF: Development Framework for Processor Architecture Implementation and Evaluation"
  Proceedings of IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME), pp. 37-40, Madonna Di Campiglio, Italy, July 3-7 2011.
• A. Bardizbanyan, M. Själander, and P. Larsson-Edefors
  "Reconfigurable Instruction Decoding for a Wide-Control-Word Processor"
  Proceedings of Reconfigurable Architectures Workshop (RAW), IEEE International Symposium on Parallel and Distributed Processing (IPDPS), pp. 317-320, Anchorage, Alaska, USA, May 16-17 2011.

2010

• T. T. Hoang, M. Själander, and P. Larsson-Edefors
  "High-Speed, Energy-Efficient 2-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit"
  IEEE Transactions on Circuits and Systems, I: Regular papers, vol. 57, no. 12, pp. 3073-3081, Dec. 2010
• T. T. Hoang, U. Jälmbrant, E. der Hagopian, K. P. Subramaniyan, M. Själander, and P. Larsson-Edefors
  "Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect"
  Proceedings of IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 55-62, Rennes, France, July 7-9 2010.
• M. Waqar, T. T. Hoang and P. Larsson-Edefors
  "Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor"
  Proceedings of Euromicro Conference on Digital System Design (DSD), Lille, France, Sept. 1-3 2010.
• E. Ryman, P. Larsson-Edefors, K. Subramaniyan, M. Islam, T. Hoang, and M. Själander
  "FlexTools: Design Space Exploration Tool Chain from C to Physical Implementation"
  Presented at CDNLive! EMEA 2010, Munich, Germany, May 4-6 2010
• Babak Hidaji, Salar Alipour, Jacob Lidman, Kasyab P. Subramaniyan, and Per Larsson-Edefors
  "Datapath Interconnect Optimization Engine for Energy-Efficient FlexCore Configurations"
  Presented at Swedish System-on-Chip Conference, Kolmården, Sweden, May 3-4, 2010

2009

• Martin Thuresson, Magnus Själander, Magnus Bjök, Lars Svensson,
  Per Larsson-Edefors, and Per Stenstrom
  "FlexCore: Utilizing Exposed Datapath Control for Efficient Computing"
  Springer Journal of Signal Processing Systems, vol. 57, no. 1, pp. 5-19, October 2009
• M. Själander and P. Larsson-Edefors
  "Multiplication Acceleration through Twin Precision"
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 9, pp. 1233 - 46, September 2009.
• T. T. Hoang, M. Själander, and P. Larsson-Edefors
  "High-Speed, Energy-Efficient 2-Cycle Multiply-Accumulate Architecture"
  Proceedings of IEEE International System on Chip Conference (SoCC), Belfast, UK, September 9-11, 2009
• T. T. Hoang, M. Själander, and P. Larsson-Edefors
  "Double Throughput Multiply-Accumulate Unit for FlexCore Processor Enhancements"
  Reconfigurable Architectures Workshop (RAW), Proceedings of IEEE International Symposium on Parallel and Distributed Processing (IPDPS), Rome, Italy, May 23-29 2009
• T. Schilling, M. Själander, and P. Larsson-Edefors
  "Scheduling for an Embedded Architecture with a Flexible Datapath"
  Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 151-6, Tampa, USA, May 13-15 2009
• T. T. Hoang, M. Själander, and P. Larsson-Edefors
  "Ultra-Low-Power 2-Cycle Multiply-Accumulate Architecture"
  Presented at Swedish System-on-Chip Conference, Arild, May 4-5 2009
• U. Jälmbrant, E. der Hagopian, M. Själander, and P. Larsson-Edefors
  "Design-Time Scheduling for Processor Exploration"
  Presented at Swedish System-on-Chip Conference, Arild, May 4-5 2009

2008

• Martin Thuresson and Per Stenstrom
  "Accommodation of the Bandwidth of Large Cache Blocks using Cache/Memory Link Compression"
  Proceedings of IEEE International Conference on Parallel Processing, September 09-11, 2008
• Magnus Själander and Per Larsson-Edefors
  "High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Reduction Tree"
  Proceedings of IEEE International Conference on Electronics, Circuits and Systems,
  St. Julians, Malta, 31st August - 3 September, 2008
• Martin Thuresson and Per Stenstrom
  "Memory Link Compression Schemes: A Value Locality Perspective"
  IEEE Transactions on Computers, Volume 57, Issue 7, July 2008
• T. Hoang, M. Själander, and P. Larsson-Edefors
  Double Throughput MAC for Performance Enhancement of the FlexCore Processor
  Presented at Swedish System-on-Chip Conference, Gnesta, May 5-6 2008
• Magnus Själander and Per Larsson-Edefors
  "The Case for HPM-Based Baugh-Wooley Multipliers"
  Department of Computer Science and Engineering, Chalmers University of Technology, Technical Report 08-8,
  Göteborg, Sweden, March 4, 2008

2007

• Martin Thuresson, Magnus Själander, Magnus Bjök, Lars Svensson,
  Per Larsson-Edefors, and Per Stenstrom
  "Utilizing Exposed Datapath for Efficient Computing"
  Proceedings of IEEE International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS VII), Samos, Greece, July 16-19, 2007
• Magnus Själander, Per Larsson-Edefors, and Magnus Björk
  "A Flexible Datapath Interconnect for Embedded Applications"
  Proceedings of IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brazil, May 9-11 2007

2006

• Magnus Björk, Magnus Själander, Lars Svensson, Martin Thuresson
  John Hughes, Kjell Jeppson, Jonas Karlsson, Per Larsson-Edefors, Mary Sheeran, and Per Stenstrom
  "Exposed datapath for efficient computing"
  Technical Report 2006-20, Chalmers University of Technology, Department of Computer Science and Engineering, December 2006
• Martin Thuresson and Per Stenstrom
  "Scalable Value-Cache Based Compression Schemes for Multiprocessors"
  Proceedings of IEEE International Symposium on Computer Architecture and High Performance Computing,
  Ouro Preto, Brazil, Oct, 2006
• Martin Thuresson
  Licentiate thesis on "Compression Techniques for Code Size and Data Bandwidth Reduction"
  ISSN: 1652-876X, Technical Report 14L, Chalmers University of Technology
• Magnus Själander
  Licentiate thesis on "Efficient Reconfigurable Multipliers Based on the Twin-Precision Technique"
  ISSN: 1652-876X, Technical Report 12L, Chalmers University of Technology
• Magnus Björk, Magnus Själander, Lars Svensson, Martin Thuresson
  John Hughes, Kjell Jeppson, Jonas Karlsson, Per Larsson-Edefors, Mary Sheeran, and Per Stenstrom
  "Exposed datapath for efficient computing"
  Proceedings of HiPEAC Workshop on Reconfigurable Computing, Ghent, Belgium, January 28-30 2006
• Martin Brinck, Kristian Eklund, Magnus Själander, and Per Larsson-Edefors
  "An Efficient FFT Engine Based on Twin-Precision Computation"
  Presented at Swedish System-on-Chip Conference, 2006

2005

• Magnus Själander, Martin Thuresson, Per Larsson-Edefors, and Per Stenström
  "FlexSoC - Past, Present & Future", (Poster), ISBN: 90 382 0802 2
  Presented at ACACES, L'Aquila, Italy, July 24-30, 2005
• Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, and Henrik Eriksson
  "A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating"
  Proceedings of IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23-26, 2005
• Martin Thuresson and Per Stenstrom
  "Evaluation of Extended Dictionary-Based Static Code Compression Schemes"
  Proceedings of IEEE Computer Frontiers 2005, Ischia, Italy, May 4-6th, 2005
• Magnus Själander and Per Larsson-Edefors
  "A Power-Efficient and Versatile Modified-Booth Multiplier"
  Presented at Swedish System-on-Chip Conferences, Tammsvik, Sweden, April 18-19, 2005

2004

• Magnus Själander, Henrik Eriksson, and Per Larsson-Edefors
  "An Efficient Twin-Precision Multiplier"
  Proceedings of IEEE International Conference on Computer Design, San Jose, California, Oct 11-13, 2004
• John Hughes, Kjell Jeppson, Per Larsson-Edefors, Mary Sheeran, Per Stenström, and Lars "J" Svensson
  "FlexSoC"
  Presented at Swedish System-on-Chip Conference, Båstad, Sweden, April 13-14, 2004

2003

• John Hughes, Kjell Jeppson, Per Larsson-Edefors, Mary Sheeran, Per Stenström, and Lars "J" Svensson
  "FlexSoC: Combining Flexibility and Efficiency in SoC Designs"
  Proceedings of the IEEE NorChip Conference, Riga, Latvia, Nov 10-11, 2003.

Master's theses

• Ahmed Ibrahim "Accelerator Integration in FlexCore Processor"
  Master's Thesis, Chalmers University, 2013
• Kashan Khurshid Ansari "Microcode Optimization in FlexCore Compiler"
  Master's Thesis, Chalmers University, 2012
• Vahid Saljooghi "Development and Integration of Level-1 Cache RTL Modeli"
  Master's Thesis, Chalmers University, 2012
• Nikita Frolov "An Approach to Scheduling in a Hardware-Software Co-Design Toolchain"
  Master's Thesis, Chalmers University, 2011
• Salar Alipour and Babak Hidaji
  "Optimization Engine for the FlexTools Design Space Exploration Platform"
  Master's Thesis, Chalmers University, 2011
• Vineeth Saseendran and Donatas Siaudinis
  "Power Gating of the FlexCore Processor"
  Master's Thesis, Chalmers University, 2010
• Taoyong Yang
  "Cryptography Acceleration in the FlexCore processor"
  Master's Thesis, Chalmers University, 2010
• Abdul Rehman Buzdar
  "Instruction Decoder design for the FlexCore Processor"
  Master's Thesis, Chalmers University, 2010
• Syed Minhaj Hassan
  "Complete RTL Implementation of Baseline FlexCore Processor"
  Master's Thesis, Chalmers University, 2009
• Ulf Jälmbrant and Erik der Hagopian
  "Improved configurability with FlexSoC"
  Master's Thesis, Chalmers University, 2009
• Thomas Schilling
  "Instruction Scheduling for an Exposed Control Architecture"
  Master's Thesis, Chalmers University, 2008
• Jonas Ferry
  "A Comparison Between the two Synthesizable VHDL Models MIPS-RISC and MIPS-NISC"
  Master's Thesis, Chalmers University, 2008
• Erik Ryman
  "FPGA Implmentation of a FlexCore Memory Environment"
  Master's Thesis, Chalmers University, 2007
• Martin Brink and Kristian Eklund
  "A Flexible FFT/DCT Engine Using the Twin-Precision Technique"
  Master's Thesis, Chalmers University, 2006
• Jan Mårts and Tomas Carlqvist
  "A Hardware Audio Decoder Using Flexible Datapaths"
  Master's Thesis, Chalmers University, 2006
• Michael Pellauer
  CoreLoom:"A Semantic Model for Fine-Grained Flexible Datapaths"
  Master's Thesis, Chalmers University, 2004 Thesis, presentation, source code

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