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The group runs a weekly seminar series, covering papers,
projects, and events related with our research. These seminars
are open to anyone on Chalmers or GU who wishes to attend.
Seminars 2008
Current seminar series coordinator: Daniel Cederman.
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iCalendar |
RSS Feed |
| Date | Time | Location | Speaker | Refreshment Organizer | Title + Abstract |
| Tue, Nov 11 | 10.00 | Conference Room | Fu Zhang | Nhan |
Travel report from SRDS 08
Zhang will deliver a travel report from his visit at the 27th IEEE International Symposium on Reliable Distributed Systems.
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| Tue, Nov 4 | 10.00 | Conference Room | Philippas Tsigas | Zhang |
The Synchronization Power of Coalesced Memory Acceses
Multicore processor architectures have established themselves as the new generation of processor architectures. As part of the one core to many cores
evolution, memory access mechanisms have advanced rapidly. Several new memory access mechanisms have been implemented in many modern commodity multicore
processors. Memory access mechanisms, by devising how processing cores access the shared memory, directly influence the synchronization capabilities of
the multicore processors. Therefore, it is crucial to investigate the synchronization power of these new memory access mechanisms. This paper
investigates the synchronization power of coalesced memory accesses, a family of memory access mechanisms introduced in recent large multicore
architectures like the CUDA graphics processors. We first design three memory access models to capture the fundamental features of the new memory access
mechanisms. Subsequently, we prove the exact synchronization power of these models in terms of their consensus numbers. These tight results show that the
coalesced memory access mechanisms can facilitate strong synchronization between the threads of multicore processors, without the need of synchronization
primitives other than reads and writes. In the case of the contemporary CUDA processors, our results imply that the coalesced memory access mechanisms
have consensus numbers up to sixteen.
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| Tue, Oct 21 | 10.30 | EE | Jerker Bengtsson | Daniel |
A Domain-specific Approach for Software Development on Manycore Platforms
To be able to handle the rapidly increasing programming complexity of manycore processors, we argue that domain specic development
tools are needed. The signal processing required
in radio base stations (RBS), is naturally highly parallel and described by computations
on streams of data. Each module in the gure encapsulates a set of functions, further exposing more
pipeline-, data- and task level parallelism as a function of the number of connected users. Many radio channels have to be processed concurrently, each
including fast and adaptive coding and decoding of
digital signals. Hard real-time constraints imply that
parallel hardware, including processors and accelera-
tors is a prerequisite for coping with these tasks in a
satisfactory manner.
One candidate technology for building baseband
platforms is manycores. Based on the specied timing constraints and dierent types and levels of parallelism in this specic type of application, we are
especially interested in manycores where cores:
- are many to the number
- are tightly coupled via a decentralized interconnection
network and offer low core send- and receive occupancy
- have individual instruction execution ability
- allow the programmer to orchestrate the transactions
between local and global memories
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| tue, sep 30 | 10.00 | Conference room | Zhang | - |
Mitigating Distributed Denial of Service Attacks in
Multiparty Applications in the Presence of Clock Drifts
A weak point in network-based applications is that they
commonly open some known communication port(s), mak-
ing themselves targets for denial of service (DoS) attacks.
Considering adversaries that can eavesdrop and launch di-
rected DoS attacks to the applications. open ports, solu-
tions based on pseudo-randomport-hopping have been sug-
gested. As port-hopping needs that the communicating par-
ties hop in a synchronized manner, these solutions suggest
acknowledgment-based protocols between a client-server
pair or assume the presence of synchronized clocks. Ac-
knowledgments, if lost, can cause a port to be open for a
longer time and thus be vulnerable to DoS attacks; Time
servers for synchronizing clocks can become targets to DoS
attack themselves.
Here we study the case where the communicating parties
have clocks with rate drift, which is common in networking.
We propose an algorithm, BIGWHEEL, for servers to com-
municate with multiple clients in a port-hopping manner,
thus enabling support to multi-party applications as well.
The algorithm does not rely on the server having a fixed
port open in the beginning, neither does it require from the
client to get a .first-contact. port from a third party. We
also present an adaptive algorithm, HOPERAA, for hop-
ping in the presence of clock-drift, as well as the analysis
and evaluation of the methods. The solutions are simple,
based on each client interacting with the server indepen-
dently of the other clients, without the need of acknowledg-
ments or time server. Provided that one has an estimation
of the time it takes for the adversary to detect that a port is
open and launch an attack, the method we propose does not
make it possible to the eavesdropping adversary to launch
an attack directed to the application.s open port(s).
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| tue, sep 16 | 10.00 | 5453 | Elad Schiller | Georgios |
Strategies for Repeated Games with Subsystem Takeovers
Implementable by Deterministic and Self-Stabilizing Automata
Systems of selfish-computers, such as the Internet, are subject
to transient faults due to hardware/software temporal
malfunctions; just as the society is subjected to human mistakes
due to a moment of weakness. Game theory uses
punishment for deterring improper behavior. Due to faults,
selfish-computers may punish well-behaved ones. This is one
of the key motivations for forgiveness that follows any effective
and credible punishment. Therefore, unplanned punishments
must be proven to have ceased in order to avoid
infinite cycles of unsynchronized behavior of .tit for tat..
We investigate another aspect of selfish-computer systems.
We consider the possibility of subsystem takeover, say, by
the use of hostile malware. The takeover may lead to joint
deviations coordinated by an arbitrary selfish-computer that
controls an unknown group of subordinate computers.
We present strategies that deter the coordinator (and its
subordinates) from deviating in infinitely repeated games.
We construct deterministic and finite automata that implement
these strategies with optimal complexity. Moreover,
we prove that all unplanned punishments eventually cease
by showing that the automata can recover from transient
faults.
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| tue, sep 2 | 10.00 | Conference room | Daniel Cederman | Marina |
A Practical Quicksort Algorithm for Graphics Processors[ESA08]
Daniel will give a rehearsal of the talk he will give at ESA.
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| ti, jun 24 | 10.00 | Conference room | Nichlas Ernberg | Elad | Parallel Programming and Case Studies using Intel Thread Building Blocks
Nichlas will present his masters thesis on "Parallel Programming and Case Studies Using Intel Thread Building Blocks".
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| fr, jun 13 | 10.00 | Conference room | Daniel Cederman | - | On Dynamic Load Balancing on Graphics Processors[GH08]
Daniel will give a rehearsal of the talk he will give at Graphics Hardware in Sarajevo.
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| må, jun 9 | 10.00 | Conference room | Daniel Cederman | - | A Practical Quicksort Algorithm for Graphics Processors[AFAPA]
Daniel will give a rehearsal of the talk he will give at the AFAPA summer school.
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| ti, maj 20 | 10.00 | Conference room | Zahid Iqbal | Georgios | Self-stabilizing Media Access in Sensor Networks
We consider the problem of accessing a single shared media. We assume a
fixed communication graph and a globally synchronized common pulse (but no
clock synchronization). We implement a silent self-stabilizing algorithm
that allocates timeslots in which the nodes broadcast. We empirically
demonstrate that within a constant number of communication rounds, a large
number of nodes communicate successfully, i.e. without collisions.
Moreover, the ratio between successful and unsuccessful broadcasts rapidly
approaches to 1. The experiments were carried out using the TOSSIM
simulator.
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| ti, maj 13 | 10.00 | Conference room | Philippas Tsigas | Zhang | Wait-Free Programming for General Purpose Computations on Graphical Processors
The fact that graphics processors (GPUs) are today’s
most powerful computational hardware for the dollar has
motivated researchers to utilize the ubiquitous and powerful GPUs for general-purpose computing. Recent GPUs
feature the single-program multiple-data (SPMD) multicore
architecture instead of the single-instruction multiple-data
(SIMD). However, unlike CPUs, GPUs devote their transistors mainly to data processing rather than data caching and
flow control, and consequently most of the powerful GPUs
with many cores do not support any synchronization mechanisms between their cores. This prevents GPUs from being
deployed more widely for general-purpose computing.
This paper aims at bridging the gap between the lack
of synchronization mechanisms in recent GPU architectures and the need of synchronization mechanisms in parallel
applications. Based on the intrinsic features of recent
GPU architectures, we construct strong synchronization objects like wait-free and t-resilient
read-modify-write objects for a general model of recent GPU architectures without
strong hardware synchronization primitives like test-and-set
and compare-and-swap. Accesses to the wait-free objects have
time complexity O(N), whether N is the number of processes.
Our result demonstrates that it is possible to construct
wait-free synchronization mechanisms for GPUs without the need of strong synchronization primitives
in hardware and that wait-free programming is possible for
GPUs.
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| ti, apr 29 | 10.00 | Conference room | Gonzalo Cornejo and Patrik Sellin | Elad | Visualizing sensor network executions - a visualization extension to TOSSIM
This document describes a project about developing a visual front-end
for a command line simulator named TOSSIM. TOSSIM is a discrete event
simulator for TinyOS driven wireless sensor network.
The problems encountered in our early experience debugging with TOSSIM
was the key motivation for developing a visualizer for TOSSIM. We
wanted to develop a tool that could easily filter debug messages, give
a global perspective of a running application and be able to control
the simulation as much as possible from a GUI instead of modifying a
script. To quickly and efficiently remove bugs and to get an improved
intuition of how their protocol behaves before testing it on a live
network. This application is called VET and it's the abbreviation of
Visualization Extension to TOSSIM.
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| ti, apr 15 | 10.00 | Conference room | Philippas Tsigas | Daniel | Travel report from PPoPP '08
Philippas Tsigas will give a travel report of his visit to PPoPP '08.
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| ti, apr 8 | 10.00 | Conference room | Zhang Fu | Philippas | Mitigating DoS attacks
Zhang will give a short overview of denial of service attacks and some
existing methods for countering DoS attacks. Then he will present the
methods mitigating the DoS attacks in the application layer including his
current work.
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| ti, apr 1 | 10.00 | Conference room | Andreas Karlsson and Kristoffer Wilhelmson | Lei | Vector-based map-cutting for server-based navigation systems
Andreas Karlsson and Kristoffer Wilhelmson will present their master thesis
"Vector-based map-cutting for server-based navigation systems".
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| ti, mar 18 | 10.00 | Conference room | Daniel Cederman | Georgios | Quicksort on GPU:s[paper,project]
In this talk Daniel will present GPU-Quicksort, an efficient Quicksort algorithm suitable
for highly parallel multi-core graphics processors. Quicksort has previously been considered
an inefficient sorting solution for graphics processors, but we show that in CUDA,
NVIDIA's programming platform for general purpose computations on graphical processors,
GPU-Quicksort performs better than the fastest known sorting implementations for
graphics processors, such as radix and bitonic sort. Quicksort can thus be seen as a viable
alternative for sorting large quantities of data on graphics processors.
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| ti, mar 11 | 10.00 | Conference room | Andreas Larsson | - | Sensor networks, an overview with focus on security
Andreas Larsson gives an introduction to sensor networks, their
possibilites, limitations and examples of uses. If will focus a bit on
security and robustness. It is a rehearsal of the talk he will give in the
Security Arena seminar series.
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| ti, mar 4 | 10.00 | Conference room | Georgios Georgiadis | Zhang Fu | Travel report from DYNAMO meeting[workshop]
In this talk Giorgos will present a travel report from the recent DYNAMO Meeting in Freiburg,
with extended overviews of selected presentations.
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| on, jan 9 | 10.15 | Conference room | Fuad Tabba | Marina | NZTM: Nonblocking Zero-Indirection Transactional Memory[paper,introduction,presentation]
This talk is about work in progress on NZTM, a nonblocking, zero-indirection object-based hybrid transactional memory system. NZTM can execute transactions using best-effort hardware transactional memory if it is available and effective, but can execute transactions using NZSTM, our compatible software transactional memory system otherwise. Previous nonblocking software and hybrid transactional memory implementations pay a significant performance cost in the common case, as compared to simpler, blocking ones. However, blocking is problematic in some cases and unacceptable in others. NZTM is nonblocking, but shares the advantages of recent blocking STM proposals in the common case: it stores object data "in place", thus avoiding the costly levels of indirection in previous nonblocking STMs, and improves cache performance by collocating object metadata with the data it controls.
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Archived Seminars
Use the following links to get access to the seminar schedules
of previous years:
2008,
2007,
2006,
2005,
2004,
2003,
2002,
2001,
2000.
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