Hardware Description and Verification

Labs and Exams

For the Labs: you should work together in pairs. For the Exams: this is an exam, so you are to work on your own and are not allowed to cooperate! See this page about cheating, which concerns both labs and exams.

The assignments should be submitted through the Fire system. Instructions for users.

There is a page with guidelines for design and verification. Make sure to read it before working on the labs.

• VHDL/PSL Lab 2011. Partial solution stopwatchRemoved.vhdl. Here is an outline of the testbench. You are required to follow this stucture.
  Deadline: Friday March 30, 23:59

• VHDL/PSL Exam 2012. Partial solution fifoRemoved.vhdl.
  Deadline: Tuesday April 24, 18:00

• Lava Lab 2012. Partial solution LavaLabRemoved12.hs.
  Deadline: Tuesday May 8, 23:59

• Lava Exam 2012. Extra files EFile12.hs, DrawPP12.hs and LavaExamRemoved12.hs.
  Deadline: Friday May 18, 18:00

Written exam

The written exam will take place on the afternoon of May 24 2012. You will need to register about a month in advance.

The retake of the written exam is on the afternoon of August 31 2012.