Energy estimation at architectural level is vital
since early design decisions have the greatest impact on the
final implementation of an electronic system. It is, however, a
particular challenge to perform energy evaluations for processors
since they are based on a mix of complex software and complex
hardware. While the software presents the processor designer
with methodological problems related to, e.g., choice of benchmarks,
process technology scaling has made implementation properties
depend very strongly on, e.g., different circuit optimizations
such as those used during timing closure. However tempting
it is to modularize the hardware of a pipeline, this common
method of using decoupled building blocks for energy estimation is
bound to neglect implementation and integration aspects that are
increasingly vital in scaled technologies.
Here we publish the open-source package of CREEP, an energy
evaluation framework for processor pipelines, which at its core
has an accurate 65-nm CMOS implementation model of different
configurations of a MIPS-I-like pipeline including level-1 caches.
The most straightforward mode of operation is to use CREEP with
already estimated post-layout data for which the user can vary
configuration parameters mainly related to cache settings.
However, since the CREEP package below is shipped with pipeline
RTL code, it is also possible for an advanced user to modify the
pipeline to include other pipeline features or retarget the RTL
code to a different process technology.
Below we provide an opportunity for
the public to download the CREEP package and related documents:
Webmaster: Prof. Per Larsson-Edefors
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