Curriculum Vitae of Lars Svensson

August 2010

Synopsis

I began my college studies at Lund University, Sweden, in 1978, and received the ”Civilingenjör” (MSEE) degree in 1983. I spent the academic year of 1979-1980 in the Swedish Army, doing my conscription service. I then entered the Graduate program at the Department of Applied Electronics, Lund University. In 1986, I received the ”Teknisk Licenciat” degree.

From 1987 to 1989, I was an exchange visitor at the University of California, Berkeley, spending half of my time in Lund and half of it in Berkeley. I completed my thesis in 1990 and received the Ph.D. degree, also from Lund University.

From 1990 to the end of 1992, I was with the VSDM division of IMEC, Belgium.

From 1993 until the end of 1997, I was a Research Scientist at the Information Sciences Institute of the University of Southern California (ISI/USC).

From the beginning of 1998 until March 2000, I was with Ericsson Mobile Communications, in Lund, Sweden, holding a position as Senior Specialist in Low-Power Switching Systems.

From April 2000 until the end of 2001, I was with SwitchCore AB, as the Technical Director and General Manager of the Göteborg office.

From January 2002 until present, I have been with the Department of Computer Engineering of Chalmers University, first as the Project Leader of the Chalmers Integrated Electronic Systems Initiative, and then (from June 2005) as an Associate Professor. In November 2003, I was appointed Honorary Associate Professor (”Docent”) in Integrated Electronic Systems. From January to June 2005, I took a leave of absence to take classes in business administration at the Business School at Göteborg University.

Research

Lund University

Initially, my main research activities were in the design of analog and analog/digital integrated circuits. During my first year at Applied Electronics, I was responsible for the layout of a switched-capacitor high-frequency prescaler in a CMOS-SOI process. Later, I also designed a pad library for a 3um n-well process.

From 1984, I worked on low-power sigma-delta A-to-D converters, which resulted in my Licenciat degree in 1986.

From 1987 until 1990, I worked on CAD tools for the design of application-specific signal processors, using a telecommunication application as a driver. This work was mainly carried out at UC Berkeley; it eventually led up to my Ph.D. degree [3]. I also co-wrote two chapters of a monograph on the CAD system which was one of the results of the project [4].

IMEC

From 1990 until the end of 1992, I worked in the Cathedral high-level synthesis group at IMEC, mainly dealing with research project coordination. My first task was to be the coordinator of an ESPRIT project on high-level synthesis, involving seven academic partners in seven countries. The project ended in the beginning of 1992; I co-edited a monograph of the results of this project [5].

I was later responsible for the IMEC contacts with the ESPRIT program ”Open Microprocessor systems Initiative”, OMI. I was also the head of a group working on design representation for high-level synthesis. This involved design and implementation of software libraries, intended as a ”backbone” for the future high-level synthesis tools of VSDM.

USC/ISI

I worked full-time on various aspects of energy-recovery, or ”adiabatic,” CMOS circuits throughout my stay at USC/ISI. The topic involves ways to reduce energy dissipation in switching circuits below the CV2 limit.

While at ISI, I was a co-author of several influential publications on energy-recovery CMOS. We published the first experimental power dissipation figures for a switching circuit based on energy recovery [6], as well as the first report of a working sequential fully-adiabatic logic circuit [7]. We were the first to describe the important influence of the power supply on the overall power efficiency of energy-recovery circuits [6]; I was later a co-inventor of an all-resonant power supply with unsurpassed efficiency [15, 18]. We summarized the first part of our work in an early overview article [12].

Much initial investigation of energy-recovery techniques was based on the premise of reversible computing, a theoretical requirement for the very lowest dissipation. Based on my investigations of a simple adder circuit, we concluded that the cost of fully-reversible circuits in present-day CMOS is likely to be very high, both in area and processing speed [10]. Our subsequent investigations of reversible circuits have been quite limited [22], but the topic is still theoretically interesting.

A major part of my work at USC/ISI went into the design and implementation of AC-1, the first complete microprocessor to use energy-recovery techniques to decrease power dissipation. The processor has been the subject of several publications [20, 21]. The lessons learned were applied in a follow-up project, which was however not finished until after I had left [27]. The same design principles were also used in a memory design [26].

Stepwise charging, which uses capacitive rather than inductive components for energy storage, was an area of particular emphasis of my work at ISI. I invented the basic technique [8, 9], led the investigation of some theoretical aspects [19], and implemented several circuits based on the technique. USC filed for a patent for the invention [14] (later re-issued [33, 55]) and secured patent positions for several extensions, one of which has resulted in another patent [39, 46, 53, 59].

I pursued two main application areas for the stepwise-charging technique. Signal drivers for inter-chip signalling was the initial one. I designed a medium-speed driver with dissipation between 50% and 70% of CV2, the lower limit for conventional drivers [17]. Further developments of the same design focused on higher speeds and smaller loads; the results have not yet been published.

The second application area was that of LCD drivers. I investigated ways to use energy-recovery principles to save power in the column drivers of an active-matrix liquid-crystal display, and built several test chips to verify the theoretical findings. Because of intellectual property concerns, only partial results were published [25]; in addition, three patents has been issued [30, 56, 72], and USC has patent positions for further aspects of this work. This work was passed on to MicroDisplay Corporation, a startup company working with USC/ISI; a similar LCD driver were used in their products.

After resigning from USC/ISI, I have continued to receive invitations to speak about our work there. Scheduling restrictions have prevented me from accepting most of these invitations. I have also written the adiabatic-charging chapter of a reference book on low-power electronic design [49]. Google Scholar finds almost 400 citations of our publications in this area.

Ericsson

I worked on various aspects of low-power digital circuits, but mostly on the mixed-signal problem complex. My investigations focused on ways to design digital circuits for minimal generation of high harmonics [23] and for minimal peak supply currents. I filed several related invention disclosures for subsequent patent treatment, some of which have resulted in issued patents [29, 31, 38, 48, 60]. In related work, I worked with a colleague on ways to relax symmetry requirements on clock-distribution networks, while maintaining or increasing performance and using design headroom to reduce electromagnetic emissions from the clock networks; this work resulted in one patent [42, 45]. A circuit design for a skew-tolerant flip-flop was also patented [51]. We also investigated some more conventional clock-dithering methods, resulting in two issued patents [32, 47].

I also worked on general digital-system-design issues. In a project with Högskolan i Karlskrona-Ronneby (now Blekinge Tekniska Högskola), we investigated digital-filter design methods for cases when ”textbook” transfer functions are unsuitable. This work has resulted in two journal articles [28, 41].

The working environment at Ericsson was conducive to creativity and cross-disciplinary work. With my co-workers, I filed several disclosures for communication-system-level inventions. Several of these disclosures have resulted in issued patents [35, 54, 36, 37].

SwitchCore

My first task at SwitchCore was to recruit a research team for physical-level signalling, to prepare for a subsequent product design effort. I then led the technical work in system identification, algorithm design, and implementation of critical function blocks for high-speed signalling on twisted-pair cables.

The nature of my work at SwitchCore did not tend to the publishable. The exception was a journal article on the influence of random electrical-parameter fluctuations on the circuit- and system-level performance of lossy transmission lines [34].

Chalmers

In 2003, I was the main author of a research proposal for an embedded-processor project. The main idea is to replace the fixed instruction-set architecture with a malleable hardware/software interface [44], which can be tuned to the algorithm and the datapaths at hand. The flexibility attainable with the malleable interface provides opportunities for higher performance [58, 63, 66], which compensates for the higher driven capacitance caused by the flexible interconnect.

I have also initiated investigations into the skin effect and its influence on high-speed interconnect in digital circuits [50, 52]. This work continued with a study of physically realizable, lower-order models for interconnects [57, 68]. Later work in the same project has focused on supply networks and on how to design them for different workloads [61, 64, 65].  Further investigations along these lines have been carried out in cooperation with ATMEL Norway [70, 71, 75].

Additionally, I have taken part in many technical investigations in the VLSI design group of Prof. Larsson-Edefors, on topics including multi-VT logic design [40], high-performance clock generation [43], power-gating techniques [62], and high-performance cross-correlator design [73].

Commissions of trust

From the beginning of 2006 to the end of 2007, I was a member of the Department Council of the Department of Computer Science and Engineering. During 2007, I was a member of the Program Council for the Computer-Engineering education programmes. From the beginning of 2008, I have been Head of the Division of Computer Engineering within the CSE Department at Chalmers.

I have served as the Faculty Opponent at the Ph.D. defenses of Ingemar Söderquist (Linköping University, 2002), Per Persson (Blekinge Tekniska Högskola, 2003), Daniel Wiklund (Linköping University, 2005), and Henrik Olsson (Linköping University, 2005). I have served on the Ph.D. committees of Atila Alvandpour (Linköping University, 1999), Anders Berkeman (Lund University, 2002), Oscar Gustafsson (Linköping University, 2003), Flemming Nyboe (Ørsted·DTU, 2006), Emil Axelsson (Chalmers University, 2008), Kenny Johansson (Linköping University, 2008), Benny Sällberg (Blekinge Tekniska Högskola, 2008), and Björn Nilsson (Halmstads Tekniska Högskola, 2010). I have been an external examiner of the PhD thesis of Johan Sommarek (Helsinki University of Technology, 2007). I was a co-supervisor of Anders Åhlander (Halmstads Tekniska Högskola, 2007) and of Martin Thuresson (Chalmers University of Technology, 2008).

I have served on the Technical Program Committees of the International Symposium on Low Power Electronics and Design (ISLPED) and of the International Conference on Computer Design (ICCD), and reviewed manuscripts for IEEE Transactions on Circuits and Systems, the IEEE Transactions on VLSI Systems, and the IEEE Transactions on Computers. I was the general Chair of PATMOS 2007 and the programme Chair of PATMOS 2008. I am a Co-Chair of the Logic and Circuits Track of ICCD 2007 through 2009.

From 2000 to 2002, I served as Chairman of the Steering Board of the INTELECT program, a Strategic Research Foundation (SSF) funded effort for academic research in circuit design and system integration. With approximately 40 funded students, the INTELECT program was the largest source of graduate student funding for Swedish research groups in microelectronics.  From 2003 to 2007, I was a member of the Steering Group of the STRINGENT program at Linköping University. STRINGENT was the largest of the SSF-funded successors of INTELECT.

I was the founding Chairman of the Swedish Chapter of the IEEE Solid-State Circuit Society from December 2003 to January 2005. From January 2005 to January 2006, I was a Board member of the same Chapter. From April 2004 to March 2008, I have been a Board member of the Sweden Section of the IEEE; from April 2006 to March 2008, I was the Section Chairman. I am a Senior Member of the IEEE.

Publications

[1] L. Svensson, M. Torkelson, L. Thon, and R. Jain. Implementation aspects of a decision feedback equalizer ASIC using an automatic layout generation system. Proceedings of the 1988 IEEE ISCAS, pages 585–588.

[2] L. Svensson. Channel equalizer for a digital mobile telephone using narrow-band TDMA transmission. Proceedings of the 39th IEEE VTC, pages 155-158, May 1989.

[3] L. Svensson. Implementation aspects of decision feedback equalizers for mobile telephones. Ph.D. Thesis, Lund University, Lund, June 1990.

[4] Robert W. Brodersen (ed). Anatomy of a silicon compiler. Chapter 13: Behavior and switch level simulation; Chapter 17: From C to silicon. Kluwer, 1992.

[5] Francky Catthoor and Lars Svensson (eds). Application-driven architecture synthesis. Kluwer Academic Publishers, 1993.

[6] W.C. Athas, J.G. Koller, and L. Svensson. An energy-efficient CMOS line driver using adiabatic switching. Fourth Great Lakes Symposium on VLSI, IEEE Press, pp. 159–164, Mar. 1994.

[7] W.C. Athas, L. Svensson, J.G. Koller, N. Tzartzanis, and E. Chou. A framework for practical low-power digital CMOS systems using adiabatic-switching principles. 1994 International Workshop on Low Power Design, pp. 189–194, Apr. 1994.

[8] L.”J.” Svensson and J.G. Koller. Adiabatic charging without inductors. 1994 Int. Workshop on Low-Power Design, pp. 159–164, Apr. 1994.

[9] L.”J.” Svensson and J.G. Koller. Driving a capacitive load without dissipating fCV2. 1994 Symposium on Low Power Electronics, Oct. 1994.

[10] W.C. Athas and L. Svensson. Reversible logic issues in adiabatic CMOS. Proc. of the 1994 Workshop on Physics and Computation, Nov. 1994.

[11] J.G. Koller, W.C. Athas, and L.”J.” Svensson. Thermal logic circuits. Proc. of the 1994 Workshop on Physics and Computation, Nov. 1994.

[12] W.C. Athas, L.”J.” Svensson, J.G. Koller, N. Tzartzanis, and E.Y.-C. Chou. Low-power digital systems based on adiabatic-switching principles. IEEE Trans. on VLSI Systems, Vol. 2, No. 4, pp. 398–407, Dec. 1994.

[13] A. Chandrakasan and R.W. Brodersen. Low power digital CMOS design. Chapter 6: Adiabatic switching. Kluwer Academic Publishers, 1995.

[14] L. Svensson, W.C. Athas, and J.G. Koller. System and method for power-efficient charging and discharging of a capacitive load from a single source. U.S. Patent #5,473,526. Dec 5, 1995.

[15] W.C. Athas, L.”J.” Svensson, and N. Tzartzanis. A resonant clock driver for two-phase, almost-non-overlapping clocks. In Proceedings of IEEE ISCAS ‘96, Atlanta, GA, May 12–15, 1996.

[16] W.C. Athas, W-C. Liu, L.”J.” Svensson. Energy-recovery CMOS for highly pipelined DSP Design. In Proc. of the International Symposium on Low-Power Electronics and Design, Monterey, CA, Aug 12–14, 1996.

[17] L.”J.” Svensson, W.C. Athas, and R.S-C. Wen. A sub-CV2 pad driver with 10 ns transition time. In Proc. of the International Symposium on Low-Power Electronics and Design, Monterey, CA, Aug 12–14, 1996.

[18] William Athas and Lars Svensson. Highly efficient, complementary, resonant pulse generation. U.S. Patent #5,559,478. Sept. 24, 1996.

[19] Sanjaya Dharmasena and Lars Svensson. Startup energies in energy-recovery CMOS. In Proc. of PhysComp’96, Boston, MA, Nov. 22–24, 1996.

[20] W. Athas, N. Tzartzanis, L. Svensson, L. Peterson, H. Li, X. Jiang, P. Wang, and W-C. Liu. AC-1: a clock-powered microprocessor. In Proc. of the International Symposium on Low-Power Electronics and Design, Monterey, CA, Aug 18–20, 1997.

[21] W.C. Athas, N. Tzartzanis, L.”J.” Svensson, and L. Peterson. A low-power microprocessor based on resonant energy. In IEEE Journal of Solid-State Circuits, Nov. 1997, pp. 1693–1701.

[22] C. Vieri, M. J. Ammer, A. Wakefield, L. ”J.” Svensson, W. Athas, T. Knight. Designing reversible memory. In Proceedings of the First International Conference on Unconventional Models of Computation, Auckland, NZ, Jan. 5–11, 1998.

[23] L.”J.” Svensson, Sven Mattisson. Harmonic content of digital CMOS switching waveforms. In Proceedings of the 1999 Southwest Symposium of Mixed-Signal Design, Tucson, AZ, April 11–13, 1999.

[24] L. ”J.” Svensson. Energy-recovery CMOS in the deep-submicron domain. In Proceedings of PATMOS, Kos Island, Greece, Oct. 6–8, 1999.

[25] R. Lal, W. Athas, L. Svensson. A low-power adiabatic driver system for AMLCDs. In Symposium on VLSI Circuits Digest of Technical Papers, June 15–17, 2000, pp. 198–201.

[26] N. Tzartzanis, W. Athas, L. Svensson. A low-power SRAM with resonantly powered data, address, word, and bit lines. In Proceedings of ESSCIRC 2000, Stockholm, Sweden, Sept. 19–21, 2000.

[27] W. Athas, N. Tzartzanis, W. Mao, L. Peterson, R. Lal, K. Chong, J-S Moon, L. Svensson, M. Bolotski. The design and implementation of a low-power clock-powered microprocessor. IEEE Journal of Solid-State Circuits, Nov. 2000, pp. 1561–1570.

[28] H. Dam, S. Nordebo, L. Svensson. Approximation of classical IIR filters with additional specifications. IEEE Transactions on Circuits and Systems, Part II, vol. 47, no.12, Dec. 2000, pp. 1536–1540.

[29] L. Svensson. Low-power signal driver with low harmonic content. WIPO Patent #0147119. June 28, 2001.

[30] L. Svensson, R. Lal, W. Athas. Power-efficient, pulsed driving of liquid crystal display capacitive loads to controllable voltage levels. European Patent #1114410 A. July 11, 2001.

[31] Alf Larsson, Lars Svensson. Using storage elements with multiple delay values to reduce current spikes in digital circuits. U.S. Patent #6,262,612. July 17, 2001.

[32] L. Svensson, H. Lindkvist. Apparatus and method for generating a modulated clock signal including harmonics that exhibit a known sideband configuration. WIPO Patent #0158068. Aug. 9, 2001.

[33] L. Svensson, W.C. Athas, and J.G. Koller. System and method for power-efficient charging and discharging of a capacitive load from a single source. U.S. Patent #RE37,552. Feb 19, 2002.

[34] F. Wenger, T. Gustafsson, L. Svensson. Perturbation theory for inhomogeneous transmission lines. IEEE Transactions on Circuits and Systems, Part I, vol. 49, no. 3, March 2002, pp. 289–297.

[35] Bengt Lindoff, Lars Svensson. Determining correlations of received sequences to multiple known sequences in a communications system. WIPO Patent #02054276 A. July 11, 2002.

[36] Lars Svensson, Bengt Lindoff. Radio Receiver. WIPO Patent #02056484. July 18, 2002.

[37] L. Svensson. Method and apparatus for authenticating a charging unit by a portable battery-operated electronic device. U.S. Patent #6,429,622. Aug. 6, 2002.

[38] L. Svensson. Low-power signal driver with low harmonic content. European Patent #1247340. Oct. 9, 2002.

[39] L. Svensson, W.C. Athas. Line reflection reduction with energy-recovery driver. U.S. Patent #6,486,697. Nov. 26, 2002.

[40] P. Larsson-Edefors, D. Eckerbert, H. Eriksson, and L. ”J” Svensson. Dual threshold voltage circuits in the presence of resistive interconnects. In IEEE Computer Society Annual Symposium on VLSI 2003, Tampa, Florida, USA, Feb. 20–21, 2003.

[41] H. Dam. S. Nordebo, and L. Svensson. Design of minimum-phase digital filters as the sum of two allpass functions using the cepstrum technique. IEEE Transactions on Signal Processing, vol. 51, no. 3, Mar. 2003, pp. 726–731.

[42] Lars Svensson, Hans Lindkvist. Method for reducing EMI and IR-drop in digital synchronous circuits. WIPO Patent WO03040967. May 15, 2003.

[43] D. Eckerbert, L. ”J.” Svensson, P. Larsson-Edefors. A mixed-mode delay-locked loop architecture. In Proceedings of the International Conference on Computer Design, San Jose, CA, Oct. 13–15, 2003, pp. 261–263.

[44] John Hughes, Kjell Jeppson, Per Larsson-Edefors, Mary Sheeran, Per Stenström, Lars ”J.”Svensson. FlexSoC: Combining Flexibility and Efficiency in SoC Designs. In Proceedings of the NorChip conference, Riga, Latvia, Nov 10–11, 2003.

[45] Hans Lindkvist, Lars Svensson. Method for reducing EMI and IR-drop in digital synchronous circuits. U.S. Patent #6,647,540. Nov 11, 2003.

[46] Lars G. Svensson and William C. Athas. Line reflection reduction with energy-recovery driver. U.S Patent #6,696,853. Feb 24, 2004.

[47] Lars Svensson, Hans Lindkvist. Apparatus and method for generating a modulated clock signal including harmonics that exhibit a known sideband configuration. U.S. Patent #6,711,694. March 23, 2004.

[48] Lars Svensson, Sven Mattisson. Cascode signal driver with low harmonic content. U.S. Patent #6,744,294. Jun 1, 2004.

[49] Lars Svensson. Adiabatic and clock-powered circuits. In Christian Piguet (ed): Low-Power Electronics Design. Chapter 15. CRC Press, 2004. ISBN 0849319412.

[50] Daniel A. Andersson, Lars ”J” Svensson, Per Larsson-Edefors. On skin effect in on-chip interconnects. In Proceedings of PATMOS, Santorini, Greece, Sep. 15–17, 2004.

[51] Alf Larsson, Lars Svensson. System and method for implementing a skew-tolerant true-single-phase-clocking flip-flop. U.S. Patent #6,822,495. November 23, 2004.

[52] Daniel A. Andersson, Lars ”J” Svensson, Per Larsson-Edefors. Accounting for the skin effect during repeater insertion. In Proceedings of the Great Lakes Symposium on VLSI, Chicago. April 17–19, 2005.

[53] Lars G. Svensson, William C. Athas. Line reflection reduction with energy-recovery driver. U.S. Patent #6,946,868. September 20, 2005.

[54] Lars Svensson, Bengt Lindoff. Determining correlations of received sequences to multiple known sequences in a communications system. U.S. Patent #6,954,489. October 11, 2005.

[55] L. Svensson, W.C. Athas, and J.G. Koller. System and method for power-efficient charging and discharging of a capacitive load from a single source. U.S. Patent #RE38,918. Dec 13, 2005.

[56] L. Svensson, W. Athas, R. Lal. Power-efficient, pulsed driving of capacitive loads to controllable voltage levels. U.S. Patent #6,985,142, January 10, 2006.

[57] D. Andersson, L. Svensson, P. Larsson-Edefors. Interconnect Characterization Flow for Minimal-Segment Model Selection. IEEE Norchip 06, Linköping, Sweden, Nov 19–21, 2006.

[58] M. Bjork, M. Sjalander, L. Svensson, M. Thuresson J. Hughes, K. Jeppson, J. Karlsson, P. Larsson-Edefors, M. Sheeran, and P. Stenstrom. Exposed datapath for efficient computing. HiPEAC Workshop on Reconfigurable Computing, Ghent, Belgium, January 28–30 2007.

[59] L. Svensson, W. Athas. Line reflection reduction with energy-recovery driver. U.S. Patent #7,176,712. February 13, 2007.

[60] L. Svensson, S. Mattisson. Cascode signal driver with low harmonic content. U.S. Patent #7,205,807. April 17, 2007.

[61] Daniel A. Andersson, Lars J Svensson, Per Larsson-Edefors. Toward a Systematic Sensitivity Analysis of On-Chip Power Grids Using Factor Analysis. 11th IEEE Workshop on Signal Propagation on Interconnects, Portofino, Italy, May 2007.

[62] M. Drazdziulis, P. Larsson-Edefors, and L. ”J” Svensson. Overdrive Power-Gating Techniques for Total Power Minimization. Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 125-30, Porto Alegre, Brazil, May 9–11 2007.

[63] Martin Thuresson, Magnus Sjalander, Magnus Bjork, Lars Svensson, Per Larsson-Edefors, and Per Stenstrom. FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. In Proceedings of SAMOS VII, Samos, Greece, July 16–19, 2007.

[64] Andersson, Daniel; Kristiansson, Simon; Svensson, Lars; Larsson-Edefors, Per; Jeppson, Kjell. Noise Interaction Between Power Distribution Grids and Substrate. ISQED, San Jose, CA, March 17–19, 2008.

[65] Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per. Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach. ISQED, San Jose, CA, March 17–19, 2008.

[66] M. Thuresson, M. Själander, M. Björk, L. Svensson, P. Larsson-Edefors, and P. Stenstrom.  FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. Journal of Signal Processing Systems, Springer Publishing, April 2008.

[67] K. Jeppson, L. Peterson, L. Svensson, L. Bengtsson, and P. Larsson-Edefors. A New Master’s Program in Integrated Electronic System Design. European Workshop on Microelectronics Education (EWME), Budapest, Hungary, May 28–30, 2008.

[68] Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per. Time-Domain Interconnect Characterisation Flow for Appropriate Model Segmentation. IET Computers & Digital Techniques, 2 (4) pp. 265–274.

[69] L. Svensson, W.C. Athas. Line reflection reduction with energy-recovery driver. U.S. Patent #7,504,852. March 17, 2009.

[70] Daniel A. Andersson, Björn Nilsson, Johnny Pihl, Lars “J.” Svensson, Per Larsson-Edefors. Supply Voltage Drop Study Considering On-Chip Self Inductance of a 32-bit Processor’s Power Grid. SPI’09, Strasbourg, France, May 12–15, 2009.

[71] Svensson, Lars; Pihl, Johnny; Andersson, Daniel; Nilsson, Björn; Larsson-Edefors, Per. Towards Supply-Grid-Based Derating of Timing Margins. SPI’09, Strasbourg, France, May 12–15, 2009.

[72] Svensson, Lars G.;  Athas, William C.; Lal, Rajat K. Power-efficient, pulsed driving of capacitive loads to controllable voltage levels. U.S. Patent #7,663,618. February 16, 2010.

[73] Ryman, Erik; Larsson-Edefors, Per; Svensson, Lars; Emrich, Anders; Andersson, Stefan: A Single-Chip 64 Input Low Power High Speed Cross-Correlator for Space Application. European Space Agency Microwave Technology and Techniques Workshop, Noordwijk, the Netherlands, May 10–12, 2010. 

[74] Jeppson, Kjell; Peterson, Lena; Svensson, Lars; Larsson-Edefors, Per: Implementing Constructive Alignment in a CDIO-oriented Master’s Program in Integrated Electronic System Design. Proceedings of European Workshop on Microelectronics Education, May 10–12, 2010, pp. 135–140.

[75] Svensson, Lars; Pihl, Johnny; Andersson, Daniel; Larsson-Edefors, Per. On-chip Power Supply Noise and Its Implications on Timing. Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), May 16–18, 2010, pp. 389-392.