You may also want to look at the edit window during simulation:
Using the buttons 
you can step through your VHDL code, one line at a time. This can be rather useful for debugging.
This is a really quick introduction to modelsim.
You can start modelsim with the command vsim.
Then you probably see something similar to this:
In the left hand window, you can now see the standard library. In the picture, I've opened the library ieee.std_logic_arith, and if you want to see what's in it, then right-click on it and select edit. In this window you will see what you are working with. Notice that there are tabs below it. When we open a project, or start a simulation, more tabs will appear there.
In the right window, you can type in commands to modelsim. Most commands you will need to use are also available in the menues.
ModelSim seems to have a will of its own, and sometimes, you will find these two windows stacked on top of each other, instead of next to each other.
In the file menu, choose new>project. Choose a project name and a home directory. Leave work as the default library name. The window "add items to the project" will appear. Here you can create vhdl-files, add existing files, and so on. As an example, we will add the example source from the second lecture. Donwload it and put it in the directory where you have created your project. Click on "Add Existing File". In the dialog that appears, you can locate the file using browse. Then press ok. The file will then appear in the main modelsim window. Close the "add items to the project" window (you must do that before you can do anything in the main window). The main window may now look something like the following:
Here you see all files that you have added to your project. Note the four rightmost buttons in the top. The three first of these have the following functions: compile one file, compile all files, and simulate. If you press compile all files, the blue question mark will probably turn into a red X, which means compilation error. Select compile summary in the compile-menu (or double click on the red X) to see the error messages:
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These error messages only appeared in the previous version of modelsim. The current version uses VHDL 2002 by default, so the file will go through with no problems. We include the example here to demonstrate how to track down compiling errors. If you want an example of a file which doesn't go through the compiler, we have no doubts that you'll be able to write such a file yourself :-) |
As you see, there was a large number of errors. You probably want to check the code, and see what they mean. You can do that by right clicking on the file (in the main screen), and selecting edit (or double clicking on an error message). This will show you the following window:
In line 7, the compiler expected a semicolon and found entity. Looking at the edit-window, we see that line 7 reads end entity count_pos_edges;. The error is due to the fact that modelsim by default reads all VHDL code as if it was VHDL-87, where one for instance wrote end; instead of end entity ... The solution to this is to right click on the file again, and select properties. Under the tab VHDL, there is an option labelled Use 1993 Language Syntax. Select that option, and press ok. Now recompile the file. Now you should get a green check mark, indicating successful compilation.
When we've successfully compiled our circuit we can simulate it. Press the simulate button (or select simulate in the simulate menu). The following window will appear:
The window shows all loaded libraries. All entities we declare end up in the library work, so expand that library by pressing the plus-sign next to it. Then we can select what circuit to simulate. Select add_tester and press ok. Now a new tab will appear in your main window:
Here you see a hierarchical view of the architecture we chose to simulate. At top level you see the architecture add_tester(arch) (which means the architecture arch of the entity arch_tester) which we chose to simulate. Apparently it contains instances of two architectures: add4bit(structural) and add4bit(behavioral). The structural version of add4bit contains subentities of its own.
Right click on the toplevel architecture, and select Add>Add to wave. The wave window will appear:
This window shows how the values of the different signals varies over time (like an oscilloscope). If we like to, we can add the subentities to the wave window too, just like we did with the toplevel entity. By pressing the plus sign on a composite signal (which includes std_logic_vector, signed, unsigned, and similar signals), we can show the values of each individual bit.
There are different ways to run the simulation. Here are a few:
4 us is an appropriate value.
run 4 us in the command window.
After you have run your simulation, you probably want to press the dark magnifying lens in the top of the wave window, to view your whole simulation:
Some useful things you can do now include:
You may also want to look at the edit window during simulation:
Using the buttons you can step through your VHDL code, one line at a time. This can be rather useful for debugging.
There is a lot more you can do with modelsim, but this should be enough for you to do your labs. If you play around with modelsim yourself, I'm sure you'll have no problems finding more features.
If you have any problems, come to the supervised lab times.