/* Instruction printing code for the ARM Copyright (C) 1994-2014 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) Modification by James G. Smith (jsmith@cygnus.co.uk) Adapted to dbgARM-debugger by Roger Johansson (roger@chalmers.se) This file is part of libopcodes. This library is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. It is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #include "defs.h" #include "arm.h" #include "ctype.h" #include #include static void read_memory(char * address, char *b, unsigned int size); static void print_address(long addr); static void func(const char* format, ...); /* C-library printf requires (but never uses) this */ int _sbrk( void ){return 0;} typedef int (*fprintf_ftype) (void *, const char*, ...); typedef unsigned char bfd_boolean; typedef long bfd_vma; typedef char bfd_byte; typedef int asymbol; /* FIXME: Belongs in global header. */ #ifndef strneq #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) #endif #ifndef NUM_ELEM #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) #endif #define ATTRIBUTE_UNUSED #define FALSE 0 #define TRUE 1 enum dis_insn_type { dis_noninsn, /* Not a valid instruction. */ dis_nonbranch, /* Not a branch instruction. */ dis_branch, /* Unconditional branch. */ dis_condbranch, /* Conditional branch. */ dis_jsr, /* Jump to subroutine. */ dis_condjsr, /* Conditional jump to subroutine. */ dis_dref, /* Data reference instruction. */ dis_dref2 /* Two data references in instruction. */ }; /* This struct is passed into the instruction decoding routine, and is passed back out into each callback. The various fields are used for conveying information from your main routine into your callbacks, for passing information into the instruction decoders (such as the addresses of the callback functions), or for passing information back from the instruction decoders to their callers. It must be initialized before it is first passed; this can be done by hand, or using one of the initialization macros below. */ typedef struct disassemble_info { fprintf_ftype fprintf_func; void *stream; void *application_data; /* Target description. We could replace this with a pointer to the bfd, but that would require one. There currently isn't any such requirement so to avoid introducing one we record these explicitly. */ /* The bfd_flavour. This can be bfd_target_unknown_flavour. */ //enum bfd_flavour flavour; /* The bfd_arch value. */ //enum bfd_architecture arch; /* The bfd_mach value. */ unsigned long mach; /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */ //enum bfd_endian endian; /* Endianness of code, for mixed-endian situations such as ARM BE8. */ //enum bfd_endian endian_code; /* An arch/mach-specific bitmask of selected instruction subsets, mainly for processors with run-time-switchable instruction sets. The default, zero, means that there is no constraint. CGEN-based opcodes ports may use ISA_foo masks. */ void *insn_sets; /* Some targets need information about the current section to accurately display insns. If this is NULL, the target disassembler function will have to make its best guess. */ // asection *section; int *section; /* An array of pointers to symbols either at the location being disassembled or at the start of the function being disassembled. The array is sorted so that the first symbol is intended to be the one used. The others are present for any misc. purposes. This is not set reliably, but if it is not NULL, it is correct. */ // asymbol **symbols; int **symbols; /* Number of symbols in array. */ int num_symbols; /* Symbol table provided for targets that want to look at it. This is used on Arm to find mapping symbols and determine Arm/Thumb code. */ // asymbol **symtab; int **symtab; int symtab_pos; int symtab_size; /* For use by the disassembler. The top 16 bits are reserved for public use (and are documented here). The bottom 16 bits are for the internal use of the disassembler. */ unsigned long flags; /* Set if the disassembler has determined that there are one or more relocations associated with the instruction being disassembled. */ #define INSN_HAS_RELOC (1 << 31) /* Set if the user has requested the disassembly of data as well as code. */ #define DISASSEMBLE_DATA (1 << 30) /* Set if the user has specifically set the machine type encoded in the mach field of this structure. */ #define USER_SPECIFIED_MACHINE_TYPE (1 << 29) /* Use internally by the target specific disassembly code. */ void *private_data; /* Function used to get bytes to disassemble. MEMADDR is the address of the stuff to be disassembled, MYADDR is the address to put the bytes in, and LENGTH is the number of bytes to read. INFO is a pointer to this struct. Returns an errno value or 0 for success. */ //int (*read_memory_func) // (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length, // struct disassemble_info *dinfo); /* Function which should be called if we get an error that we can't recover from. STATUS is the errno value from read_memory_func and MEMADDR is the address that we were trying to read. INFO is a pointer to this struct. */ //void (*memory_error_func) // (int status, bfd_vma memaddr, struct disassemble_info *dinfo); /* Function called to print ADDR. */ //void (*print_address_func) // (bfd_vma addr, struct disassemble_info *dinfo); /* Function called to determine if there is a symbol at the given ADDR. If there is, the function returns 1, otherwise it returns 0. This is used by ports which support an overlay manager where the overlay number is held in the top part of an address. In some circumstances we want to include the overlay number in the address, (normally because there is a symbol associated with that address), but sometimes we want to mask out the overlay bits. */ //int (* symbol_at_address_func) // (bfd_vma addr, struct disassemble_info *dinfo); /* Function called to check if a SYMBOL is can be displayed to the user. This is used by some ports that want to hide special symbols when displaying debugging outout. */ //bfd_boolean (* symbol_is_valid) // (asymbol *, struct disassemble_info *dinfo); /* These are for buffer_read_memory. */ //bfd_byte *buffer; //bfd_vma buffer_vma; //unsigned int buffer_length; /* This variable may be set by the instruction decoder. It suggests the number of bytes objdump should display on a single line. If the instruction decoder sets this, it should always set it to the same value in order to get reasonable looking output. */ int bytes_per_line; /* The next two variables control the way objdump displays the raw data. */ /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */ /* output will look like this: 00: 00000000 00000000 with the chunks displayed according to "display_endian". */ int bytes_per_chunk; // enum bfd_endian display_endian; /* Number of octets per incremented target address Normally one, but some DSPs have byte sizes of 16 or 32 bits. */ unsigned int octets_per_byte; /* The number of zeroes we want to see at the end of a section before we start skipping them. */ unsigned int skip_zeroes; /* The number of zeroes to skip at the end of a section. If the number of zeroes at the end is between SKIP_ZEROES_AT_END and SKIP_ZEROES, they will be disassembled. If there are fewer than SKIP_ZEROES_AT_END, they will be skipped. This is a heuristic attempt to avoid disassembling zeroes inserted by section alignment. */ unsigned int skip_zeroes_at_end; /* Whether the disassembler always needs the relocations. */ bfd_boolean disassembler_needs_relocs; /* Results from instruction decoders. Not all decoders yet support this information. This info is set each time an instruction is decoded, and is only valid for the last such instruction. To determine whether this decoder supports this information, set insn_info_valid to 0, decode an instruction, then check it. */ char insn_info_valid; /* Branch info has been set. */ char branch_delay_insns; /* How many sequential insn's will run before a branch takes effect. (0 = normal) */ char data_size; /* Size of data reference in insn, in bytes */ enum dis_insn_type insn_type; /* Type of instruction */ bfd_vma target; /* Target address of branch or dref, if known; zero if unknown. */ bfd_vma target2; /* Second target address for dref2 */ /* Command line options specific to the target disassembler. */ char * disassembler_options; } disassemble_info; /* Cached mapping symbol state. */ enum map_type { MAP_ARM, MAP_THUMB, MAP_DATA }; struct arm_private_data { /* The features to use when disassembling optional instructions. */ arm_feature_set features; /* Whether any mapping symbols are present in the provided symbol table. -1 if we do not know yet, otherwise 0 or 1. */ int has_mapping_symbols; /* Track the last type (although this doesn't seem to be useful) */ enum map_type last_type; /* Tracking symbol table information */ int last_mapping_sym; //bfd_vma last_mapping_addr; }; struct opcode32 { unsigned long arch; /* Architecture defining this insn. */ unsigned long value; /* If arch == 0 then value is a sentinel. */ unsigned long mask; /* Recognise insn if (op & mask) == value. */ const char * assembler; /* How to disassemble this insn. */ }; struct opcode16 { unsigned long arch; /* Architecture defining this insn. */ unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ const char *assembler; /* How to disassemble this insn. */ }; /* print_insn_coprocessor recognizes the following format control codes: %% % %c print condition code (always bits 28-31 in ARM mode) %q print shifter argument %u print condition code (unconditional in ARM mode, UNPREDICTABLE if not AL in Thumb) %A print address for ldc/stc/ldf/stf instruction %B print vstm/vldm register list %I print cirrus signed shift immediate: bits 0..3|4..6 %F print the COUNT field of a LFM/SFM instruction. %P print floating point precision in arithmetic insn %Q print floating point precision in ldf/stf insn %R print floating point rounding mode %c print as a condition code (for vsel) %r print as an ARM register %R as %<>r but r15 is UNPREDICTABLE %ru as %<>r but each u register must be unique. %d print the bitfield in decimal %k print immediate for VFPv3 conversion instruction %x print the bitfield in hex %X print the bitfield as 1 hex digit without leading "0x" %f print a floating point constant if >7 else a floating point register %w print as an iWMMXt width field - [bhwd]ss/us %g print as an iWMMXt 64-bit register %G print as an iWMMXt general purpose or control register %D print as a NEON D register %Q print as a NEON Q register %y print a single precision VFP reg. Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair %z print a double precision VFP reg Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list %'c print specified char iff bitfield is all ones %`c print specified char iff bitfield is all zeroes %?ab... select from array of values in big endian order %L print as an iWMMXt N/M width field. %Z print the Immediate of a WSHUFH instruction. %l like 'A' except use byte offsets for 'B' & 'H' versions. %i print 5-bit immediate in bits 8,3..0 (print "32" when 0) %r print register offset address for wldt/wstr instruction. */ enum opcode_sentinel_enum { SENTINEL_IWMMXT_START = 1, SENTINEL_IWMMXT_END, SENTINEL_GENERIC_START } opcode_sentinels; #define UNDEFINED_INSTRUCTION "\t\t; instruction: %0-31x" #define UNPREDICTABLE_INSTRUCTION "\t; " /* Common coprocessor opcodes shared between Arm and Thumb-2. */ static const struct opcode32 coprocessor_opcodes[] = { // // /* Floating point coprocessor (FPA) instructions. */ // {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, // {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, // {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, // {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, // {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, // {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, // {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, // {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, // {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, // {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, // {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, // // /* Register load/store. */ {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "VPUSH.F64%c\t%B"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "VSTMDB.F64%c\t%16-19r!,%B"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "VLDMDB.F64%c\t%16-19r!,%B"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "VSTMIA.F64%c\t%16-19r%21'!,%B"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "VPOP.F64%c\t%B"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "VLDMIA.F64%c\t%16-19r%21'!,%B"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "VSTR.F64%c\t%12-15,22D,%A"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "VLDR.F64%c\t%12-15,22D,%A"}, {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "VPUSH.F32%c\t%y3"}, {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "VSTMDB.F32%c\t%16-19r!,%y3"}, {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "VLDMDB.F32%c\t%16-19r!,%y3"}, {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "VSTMIA.F32%c\t%16-19r%21'!,%y3"}, {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "VPOP.F32%c\t%y3"}, {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "VLDMIA.F32%c\t%16-19r%21'!,%y3"}, {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "VSTR.F32%c\t%y1,%A"}, {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "VLDR.F32%c\t%y1,%A"}, // // {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, // {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, // {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, // {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, // // /* Data transfer between ARM and NEON registers. */ // {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, // {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, // {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, // {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, // {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, // {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, // {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, // {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, // {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, // {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, // {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, // {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, // {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, // {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, // /* Half-precision conversion instructions. */ // {FPU_VFP_EXT_ARMV8, 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, // {FPU_VFP_EXT_ARMV8, 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, // {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, // {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, // // /* Floating point coprocessor (VFP) instructions. */ {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "VMSR%c\tFPSID,%12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "VMSR%c\tFPSCR,%12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "VMSR%c\tMVFR1,%12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "VMSR%c\tMVFR0,%12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "VMSR%c\tFPEXC,%12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "VMSR%c\tFPINST,%12-15r"}, {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "VMSR%c\tFPINST2,%12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "VMRS%c\t%12-15r,FPSID"}, {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "VMRS%c\tAPSR_nzcv,FPSCR"}, {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "VMRS%c\t%12-15r,FPSCR"}, {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "VMRS%c\t%12-15r,MVFR1"}, {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "VMRS%c\t%12-15r,MVFR0"}, {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "VMRS%c\t%12-15r,FPEXC"}, {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "VMRS%c\t%12-15r,FPINST"}, {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "VMRS%c\t%12-15r,FPINST2"}, {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "VMOV%c.F32\t%z2[%21d],%12-15r"}, {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "VMOV%c.F32\t%12-15r,%z2[%21d]"}, {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "VMSR%c\t,%12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "VMRS%c\t%12-15r,"}, {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "VMOV%c\t%y2,%12-15r"}, {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "VMOV%c\t%12-15r,%y2"}, {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "VCMP%7'e%c.F32\t%y1,#0.0"}, {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "VCMP%7'e%c.F64\t%z1,#0.0"}, {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "VMOV%c.F32\t%y1,%y0"}, {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "VABS%c.F32\t%y1,%y0"}, {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "VMOV%c.F64\t%z1,%z0"}, {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "VABS%c.F64\t%z1,%z0"}, {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "VNEG%c.F32\t%y1,%y0"}, {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "VSQRT%c.F32\t%y1,%y0"}, {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "VNEG%c.F64\t%z1,%z0"}, {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "VSQRT%c.F64\t%z1,%z0"}, {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "VCVT%c.F64.F32\t%z1,%y0"}, {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "VCVT%c.F32.F64\t%y1,%z0"}, {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "VCVT%c.F32.%7?SU32\t%y1,%y0"}, {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "VCVT%c.F64.%7?SU32\t%z1,%y0"}, {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "VCMP%7'e%c.F32\t%y1,%y0"}, {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "VCMP%7'e%c.F64\t%z1,%z0"}, {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "VCVT%c.F32.%16?s%7?31%7?26\t%y1,%y1,#%5,0-3k"}, {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "VCVT%c.F64.%16?us%7?31%7?26\t%z1,%z1,#%5,0-3k"}, {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "VCVT%7`r%c.%16?SU32.F32\t%y1,%y0"}, {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "VCVT%7`r%c.%16?SU32.F64\t%y1,%z0"}, {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "VCVT%c.%16?us%7?31%7?26.F32\t%y1,%y1,#%5,0-3k"}, {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "VCVT%c.%16?us%7?31%7?26.F64\t%z1,%z1,#%5,0-3k"}, {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "VMOV%c\t%12-15r,%16-19r,%z0"}, {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "VMOV%c.F32\t%y1,#%0-3,16-19d"}, {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "VMOV%c.F64\t%z1,#%0-3,16-19d"}, {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "VMOV%c\t%y4,%12-15r,%16-19r"}, {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "VMOV%c\t%z0,%12-15r,%16-19r"}, {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "VMOV%c\t%12-15r,%16-19r,%y4"}, {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "VMLA%c.F32\t%y1,%y2,%y0"}, {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "VMLS%c.F32\t%y1,%y2,%y0"}, {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "VMLA%c.F64\t%z1,%z2,%z0"}, {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "VMLS%c.F64\t%z1,%z2,%z0"}, {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "VNMLS%c.F32\t%y1,%y2,%y0"}, {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "VNMLA%c.F32\t%y1,%y2,%y0"}, {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "VNMLS%c.F64\t%z1,%z2,%z0"}, {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "VNMLA%c.F64\t%z1,%z2,%z0"}, {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "VMUL%c.F32\t%y1,%y2,%y0"}, {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "VNMUL%c.F32\t%y1,%y2,%y0"}, {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "VMUL%c.F64\t%z1,%z2,%z0"}, {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "VNMUL%c.F64\t%z1,%z2,%z0"}, {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "VADD%c.F32\t%y1,%y2,%y0"}, {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "VSUB%c.F32\t%y1,%y2,%y0"}, {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "VADD%c.F64\t%z1,%z2,%z0"}, {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "VSUB%c.F64\t%z1,%z2,%z0"}, {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "VDIV%c.F32\t%y1,%y2,%y0"}, {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "VDIV%c.F64\t%z1,%z2,%z0"}, // // // /* VFP Fused multiply add instructions. */ // {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, // {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, // {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, // {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, // {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, // {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, // {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, // {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, // // /* FP v5. */ // {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, // {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, // {FPU_VFP_EXT_ARMV8, 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"}, // {FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"}, // {FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"}, // {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"}, // {FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, // {FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, // {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, // {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, // {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, // {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, // // /* Generic coprocessor instructions. */ // { 0, SENTINEL_GENERIC_START, 0, "" }, {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "MCRR%c\t%8-11d,%4-7d,%12-15R,%16-19r,CR%0-3d"}, {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "MRRC%c\t%8-11d,%4-7d,%12-15Ru,%16-19Ru,CR%0-3d"}, {ARM_EXT_V2, 0x0e000000, 0x0f000010, "CDP%c\t%8-11d,%20-23d,CR%12-15d,CR%16-19d,CR%0-3d,{%5-7d}"}, {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "MRC%c\t%8-11d,%21-23d,APSR_nzcv,CR%16-19d,CR%0-3d,{%5-7d}"}, {ARM_EXT_V2, 0x0e100010, 0x0f100010, "MRC%c\t%8-11d,%21-23d,%12-15r,CR%16-19d,CR%0-3d,{%5-7d}"}, {ARM_EXT_V2, 0x0e000010, 0x0f100010, "MCR%c\t%8-11d,%21-23d,%12-15R,CR%16-19d,CR%0-3d,{%5-7d}"}, {ARM_EXT_V2, 0x0c000000, 0x0e100000, "STC%22'L%c\t%8-11d,CR%12-15d,%A"}, {ARM_EXT_V2, 0x0c100000, 0x0e100000, "LDC%22'L%c\t%8-11d,CR%12-15d,%A"}, /* V6 coprocessor instructions. */ {ARM_EXT_V6, 0xfc500000, 0xfff00000, "MRRC2%c\t%8-11d,%4-7d,%12-15Ru,%16-19Ru,CR%0-3d"}, {ARM_EXT_V6, 0xfc400000, 0xfff00000, "MCRR2%c\t%8-11d,%4-7d,%12-15R,%16-19R,CR%0-3d"}, /* V5 coprocessor instructions. */ {ARM_EXT_V5, 0xfc100000, 0xfe100000, "LDC2%22'L%c\t%8-11d,CR%12-15d,%A"}, {ARM_EXT_V5, 0xfc000000, 0xfe100000, "STC2%22'L%c\t%8-11d,CR%12-15d,%A"}, {ARM_EXT_V5, 0xfe000000, 0xff000010, "CDP2%c\t%8-11d,%20-23d,CR%12-15d,CR%16-19d,CR%0-3d,{%5-7d}"}, {ARM_EXT_V5, 0xfe000010, 0xff100010, "MCR2%c\t%8-11d,%21-23d,%12-15R,CR%16-19d,CR%0-3d,{%5-7d}"}, {ARM_EXT_V5, 0xfe100010, 0xff100010, "MRC2%c\t%8-11d,%21-23d,%12-15r,CR%16-19d,CR%0-3d,{%5-7d}"}, // {0, 0, 0, 0} }; /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially ordered: they must be searched linearly from the top to obtain a correct match. */ /* print_insn_arm recognizes the following format control codes: %% % %a print address for ldr/str instruction %s print address for ldr/str halfword/signextend instruction %S like %s but allow UNPREDICTABLE addressing %b print branch destination %c print condition code (always bits 28-31) %m print register mask for ldm/stm instruction %o print operand2 (immediate or register + shift) %p print 'p' iff bits 12-15 are 15 %t print 't' iff bit 21 set and bit 24 clear %B print arm BLX(1) destination %C print the PSR sub type. %U print barrier type. %P print address for pli instruction. %r print as an ARM register %T print as an ARM register + 1 %R as %r but r15 is UNPREDICTABLE %{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE %{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE %d print the bitfield in decimal %W print the bitfield plus one in decimal %x print the bitfield in hex %X print the bitfield as 1 hex digit without leading "0x" %'c print specified char iff bitfield is all ones %`c print specified char iff bitfield is all zeroes %?ab... select from array of values in big endian order %e print arm SMI operand (bits 0..7,8..19). %E print the LSB and WIDTH fields of a BFI or BFC instruction. %V print the 16-bit immediate field of a MOVT or MOVW instruction. %R print the SPSR/CPSR or banked register of an MRS. */ /* print_insn_thumb16 recognizes the following format control codes: %S print Thumb register (bits 3..5 as high number if bit 6 set) %D print Thumb register (bits 0..2 as high number if bit 7 set) %I print bitfield as a signed decimal (top bit of range being the sign bit) %N print Thumb register mask (with LR) %O print Thumb register mask (with PC) %M print Thumb register mask %b print CZB's 6-bit unsigned branch destination %s print Thumb right-shift immediate (6..10; 0 == 32). %c print the condition code %C print the condition code, or "s" if not conditional %x print warning if conditional an not at end of IT block" %X print "\t; unpredictable " if conditional %I print IT instruction suffix and operands %W print Thumb Writeback indicator for LDMIA %r print bitfield as an ARM register %d print bitfield as a decimal %H print (bitfield * 2) as a decimal %W print (bitfield * 4) as a decimal %a print (bitfield * 4) as a pc-rel offset + decoded symbol %B print Thumb branch destination (signed displacement) %c print bitfield as a condition code %'c print specified char iff bit is one %?ab print a if bit is one else print b. */ static const struct opcode16 thumb_opcodes[] = { /* Thumb instructions. */ /* ARM V8 instructions. */ {ARM_EXT_V8, 0xbf50, 0xffff, "SEVL%c"}, {ARM_EXT_V8, 0xba80, 0xffc0, "HLT\t%0-5x"}, /* ARM V6K no-argument instructions. */ {ARM_EXT_V6K, 0xbf00, 0xffff, "NOP%c"}, {ARM_EXT_V6K, 0xbf10, 0xffff, "YIELD%c"}, {ARM_EXT_V6K, 0xbf20, 0xffff, "WFE%c"}, {ARM_EXT_V6K, 0xbf30, 0xffff, "WFI%c"}, {ARM_EXT_V6K, 0xbf40, 0xffff, "SEV%c"}, {ARM_EXT_V6K, 0xbf00, 0xff0f, "NOP%c\t{%4-7d}"}, /* ARM V6T2 instructions. */ {ARM_EXT_V6T2, 0xb900, 0xfd00, "CBNZ\t%0-2r,%b%X"}, {ARM_EXT_V6T2, 0xb100, 0xfd00, "CBZ\t%0-2r,%b%X"}, {ARM_EXT_V6T2, 0xbf00, 0xff00, "IT%I%X"}, /* ARM V6. */ {ARM_EXT_V6, 0xb660, 0xfff8, "CPSIE\t%2'a%1'i%0'f%X"}, {ARM_EXT_V6, 0xb670, 0xfff8, "CPSID\t%2'a%1'i%0'f%X"}, {ARM_EXT_V6, 0x4600, 0xffc0, "MOV%c\t%0-2r,%3-5r"}, {ARM_EXT_V6, 0xba00, 0xffc0, "REV%c\t%0-2r,%3-5r"}, {ARM_EXT_V6, 0xba40, 0xffc0, "REV16%c\t%0-2r,%3-5r"}, {ARM_EXT_V6, 0xbac0, 0xffc0, "REVSH%c\t%0-2r,%3-5r"}, {ARM_EXT_V6, 0xb650, 0xfff7, "SETEND\t%3?ble%X"}, {ARM_EXT_V6, 0xb200, 0xffc0, "SXTH%c\t%0-2r,%3-5r"}, {ARM_EXT_V6, 0xb240, 0xffc0, "SXTB%c\t%0-2r,%3-5r"}, {ARM_EXT_V6, 0xb280, 0xffc0, "UXTH%c\t%0-2r,%3-5r"}, {ARM_EXT_V6, 0xb2c0, 0xffc0, "UXTB%c\t%0-2r,%3-5r"}, /* ARM V5 ISA extends Thumb. */ {ARM_EXT_V5T, 0xbe00, 0xff00, "BKPT\t%0-7x"}, /* Is always unconditional. */ /* This is BLX(2). BLX(1) is a 32-bit instruction. */ {ARM_EXT_V5T, 0x4780, 0xff87, "BLX%c\t%3-6r%x"}, /* note: 4 bit register number. */ /* ARM V4T ISA (Thumb v1). */ {ARM_EXT_V4T, 0x46C0, 0xFFFF, "NOP%c"}, // { ARM_EXT_V4T, 0x46C0, 0xFFFF, "NOP%c\t\t\t; (mov r8, r8)" }, /* Format 4. */ {ARM_EXT_V4T, 0x4000, 0xFFC0, "AND%C\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x4040, 0xFFC0, "EOR%C\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x4080, 0xFFC0, "LSL%C\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x40C0, 0xFFC0, "LSR%C\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x4100, 0xFFC0, "ASR%C\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x4140, 0xFFC0, "ADC%C\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x4180, 0xFFC0, "SBC%C\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ROR%C\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x4200, 0xFFC0, "TST%c\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x4240, 0xFFC0, "NEG%C\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x4280, 0xFFC0, "CMP%c\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x42C0, 0xFFC0, "CMN%c\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x4300, 0xFFC0, "ORR%C\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x4340, 0xFFC0, "MUL%C\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x4380, 0xFFC0, "BIC%C\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x43C0, 0xFFC0, "MVN%C\t%0-2r,%3-5r"}, /* format 13 */ {ARM_EXT_V4T, 0xB000, 0xFF80, "ADD%c\tSP,#%0-6W"}, {ARM_EXT_V4T, 0xB080, 0xFF80, "SUB%c\tSP,#%0-6W"}, /* format 5 */ {ARM_EXT_V4T, 0x4700, 0xFF80, "BX%c\t%S%x"}, {ARM_EXT_V4T, 0x4400, 0xFF00, "ADD%c\t%D,%S"}, {ARM_EXT_V4T, 0x4500, 0xFF00, "CMP%c\t%D,%S"}, {ARM_EXT_V4T, 0x4600, 0xFF00, "MOV%c\t%D,%S"}, /* format 14 */ {ARM_EXT_V4T, 0xB400, 0xFE00, "PUSH%c\t%N"}, {ARM_EXT_V4T, 0xBC00, 0xFE00, "POP%c\t%O"}, /* format 2 */ {ARM_EXT_V4T, 0x1800, 0xFE00, "ADD%C\t%0-2r,%3-5r,%6-8r"}, {ARM_EXT_V4T, 0x1A00, 0xFE00, "SUB%C\t%0-2r,%3-5r,%6-8r"}, {ARM_EXT_V4T, 0x1C00, 0xFE00, "ADD%C\t%0-2r,%3-5r,#%6-8d"}, {ARM_EXT_V4T, 0x1E00, 0xFE00, "SUB%C\t%0-2r,%3-5r,#%6-8d"}, /* format 8 */ {ARM_EXT_V4T, 0x5200, 0xFE00, "STRH%c\t%0-2r,[%3-5r,%6-8r]"}, {ARM_EXT_V4T, 0x5A00, 0xFE00, "LDRH%c\t%0-2r,[%3-5r,%6-8r]"}, {ARM_EXT_V4T, 0x5600, 0xF600, "LDRS%11?HB%c\t%0-2r,[%3-5r,%6-8r]"}, /* format 7 */ {ARM_EXT_V4T, 0x5000, 0xFA00, "STR%10'B%c\t%0-2r,[%3-5r,%6-8r]"}, {ARM_EXT_V4T, 0x5800, 0xFA00, "LDR%10'B%c\t%0-2r,[%3-5r,%6-8r]"}, /* format 1 */ {ARM_EXT_V4T, 0x0000, 0xFFC0, "MOV%C\t%0-2r,%3-5r"}, {ARM_EXT_V4T, 0x0000, 0xF800, "LSL%C\t%0-2r,%3-5r,#%6-10d"}, {ARM_EXT_V4T, 0x0800, 0xF800, "LSR%C\t%0-2r,%3-5r,%s"}, {ARM_EXT_V4T, 0x1000, 0xF800, "ASR%C\t%0-2r,%3-5r,%s"}, /* format 3 */ {ARM_EXT_V4T, 0x2000, 0xF800, "MOV%C\t%8-10r,#%0-7d"}, {ARM_EXT_V4T, 0x2800, 0xF800, "CMP%c\t%8-10r,#%0-7d"}, {ARM_EXT_V4T, 0x3000, 0xF800, "ADD%C\t%8-10r,#%0-7d"}, {ARM_EXT_V4T, 0x3800, 0xF800, "SUB%C\t%8-10r,#%0-7d"}, /* format 6 */ {ARM_EXT_V4T, 0x4800, 0xF800, "LDR%c\t%8-10r,[PC,#%0-7W]"}, /* TODO: Disassemble PC relative "LDR rD,=" */ /* format 9 */ {ARM_EXT_V4T, 0x6000, 0xF800, "STR%c\t%0-2r,[%3-5r,#%6-10W]"}, {ARM_EXT_V4T, 0x6800, 0xF800, "LDR%c\t%0-2r,[%3-5r,#%6-10W]"}, {ARM_EXT_V4T, 0x7000, 0xF800, "STRB%c\t%0-2r,[%3-5r,#%6-10d]"}, {ARM_EXT_V4T, 0x7800, 0xF800, "LDRB%c\t%0-2r,[%3-5r,#%6-10d]"}, /* format 10 */ {ARM_EXT_V4T, 0x8000, 0xF800, "STRH%c\t%0-2r [%3-5r,#%6-10H]"}, {ARM_EXT_V4T, 0x8800, 0xF800, "LDRH%c\t%0-2r,[%3-5r,#%6-10H]"}, /* format 11 */ {ARM_EXT_V4T, 0x9000, 0xF800, "STR%c\t%8-10r,[SP,#%0-7W]"}, {ARM_EXT_V4T, 0x9800, 0xF800, "LDR%c\t%8-10r,[SP,#%0-7W]"}, /* format 12 */ {ARM_EXT_V4T, 0xA000, 0xF800, "ADD%c\t%8-10r,PC,#%0-7W\t; (ADR %8-10r, %0-7a)"}, {ARM_EXT_V4T, 0xA800, 0xF800, "ADD%c\t%8-10r,SP,#%0-7W"}, /* format 15 */ {ARM_EXT_V4T, 0xC000, 0xF800, "STMIA%c\t%8-10r!,%M"}, {ARM_EXT_V4T, 0xC800, 0xF800, "LDMIA%c\t%8-10r%W,%M"}, /* format 17 */ {ARM_EXT_V4T, 0xDF00, 0xFF00, "SVC%c\t%0-7d"}, /* format 16 */ {ARM_EXT_V4T, 0xDE00, 0xFF00, "UDF%c\t#%0-7d"}, {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, {ARM_EXT_V4T, 0xD000, 0xF000, "B%8-11c\t%0-7B%X"}, // {ARM_EXT_V4T, 0xD000, 0xF000, "B%8-11c.n\t%0-7B%X"}, /* format 18 */ {ARM_EXT_V4T, 0xE000, 0xF800, "B%c\t%0-10B%x"}, // {ARM_EXT_V4T, 0xE000, 0xF800, "B%c.n\t%0-10B%x"}, /* The E800 .. FFFF range is unconditionally redirected to the 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs are processed via that table. Thus, we can never encounter a bare "second half of BL/BLX(1)" instruction here. */ {ARM_EXT_V1, 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, {0, 0, 0, 0} }; /* Thumb32 opcodes use the same table structure as the ARM opcodes. We adopt the convention that hw1 is the high 16 bits of .value and .mask, hw2 the low 16 bits. print_insn_thumb32 recognizes the following format control codes: %% % %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] %M print a modified 12-bit immediate (same location) %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] %H print a 16-bit immediate from hw2[3:0],hw1[11:0] %S print a possibly-shifted Rm %L print address for a ldrd/strd instruction %a print the address of a plain load/store %w print the width and signedness of a core load/store %m print register mask for ldm/stm %E print the lsb and width fields of a bfc/bfi instruction %F print the lsb and width fields of a sbfx/ubfx instruction %b print a conditional branch offset %B print an unconditional branch offset %s print the shift field of an SSAT instruction %R print the rotation field of an SXT instruction %U print barrier type. %P print address for pli instruction. %c print the condition code %x print warning if conditional an not at end of IT block" %X print "\t; unpredictable " if conditional %d print bitfield in decimal %W print bitfield*4 in decimal %r print bitfield as an ARM register %R as %<>r but r15 is UNPREDICTABLE %S as %<>R but r13 is UNPREDICTABLE %c print bitfield as a condition code %'c print specified char iff bitfield is all ones %`c print specified char iff bitfield is all zeroes %?ab... select from array of values in big endian order With one exception at the bottom (done because BL and BLX(1) need to come dead last), this table was machine-sorted first in decreasing order of number of bits set in the mask, then in increasing numeric order of mask, then in increasing numeric order of opcode. This order is not the clearest for a human reader, but is guaranteed never to catch a special-case bit pattern with a more general mask, which is important, because this instruction encoding makes heavy use of special-case bit patterns. */ static const struct opcode32 thumb32_opcodes[] = { /* V8 instructions. */ {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"}, {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, /* CRC32 instructions. */ {CRC_EXT_ARMV8, 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"}, {CRC_EXT_ARMV8, 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"}, {CRC_EXT_ARMV8, 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"}, {CRC_EXT_ARMV8, 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"}, {CRC_EXT_ARMV8, 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"}, {CRC_EXT_ARMV8, 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"}, /* V7 instructions. */ {ARM_EXT_V7, 0xf910f000, 0xff70f000, "PLI%c\t%a"}, {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "DBG%c\t#%0-3d"}, {ARM_EXT_V8, 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, {ARM_EXT_V8, 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "DMB%c\t%U"}, {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "DSB%c\t%U"}, {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "ISB%c\t%U"}, {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "SDIV%c\t%8-11r,%16-19r,%0-3r"}, {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "UDIV%c\t%8-11r,%16-19r,%0-3r"}, /* Virtualization Extension instructions. */ {ARM_EXT_VIRT, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, /* We skip ERET as that is SUBS pc, lr, #0. */ /* MP Extension instructions. */ {ARM_EXT_MP, 0xf830f000, 0xff70f000, "pldw%c\t%a"}, /* Security extension instructions. */ {ARM_EXT_SEC, 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, /* Instructions defined in the basic V6T2 set. */ {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "NOP%c.W"}, {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "YIELD%c.W"}, {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "WFE%c.W"}, {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "WFI%c.W"}, {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "SEV%c.W"}, {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, {ARM_EXT_V6T2, 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "CLREX%c"}, {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, {ARM_EXT_V6T2, 0xf3e08000, 0xffe0f000, "MRS%c\t%8-11r,%D"}, {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "TBB%c\t[%16-19r,%0-3r]%x"}, {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "TBH%c\t[%16-19r,%0-3r,LSL #1]%x"}, {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "MSR%c\t%C,%16-19r"}, {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "LDREX%c\t%12-15r,[%16-19r]"}, {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "LDREX%4?HB%c\t%12-15r,[%16-19r]"}, {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "SXTH%c.W\t%8-11r,%0-3r%R"}, {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "UXTH%c.W\t%8-11r,%0-3r%R"}, {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "SXTB16%c\t%8-11r,%0-3r%R"}, {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "UXTB16%c\t%8-11r,%0-3r%R"}, {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "SXTB%c.W\t%8-11r,%0-3r%R"}, {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "UXTB%c.W\t%8-11r,%0-3r%R"}, {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "STREX%c\t%8-11r,%12-15r,[%16-19r]"}, {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "REV%c.W\t%8-11r,%16-19r"}, {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "REV16%c.W\t%8-11r,%16-19r"}, {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "RBIT%c\t%8-11r,%16-19r"}, {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "REVSH%c.W\t%8-11r,%16-19r"}, {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "CLZ%c\t%8-11r,%16-19r"}, {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "MUL%c.W\t%8-11r,%16-19r,%0-3r"}, {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "LSL%20'S%c.W\t%8-11R,%16-19R,%0-3R"}, {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "LSR%20'S%c.W\t%8-11R,%16-19R,%0-3R"}, {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "ASR%20'S%c.W\t%8-11R,%16-19R,%0-3R"}, {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ROR%20'S%c.W\t%8-11r,%16-19r,%0-3r"}, {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "STREX%4?HB%c\t%0-3r,%12-15r,[%16-19r]"}, {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"}, {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "SXTAH%c\t%8-11r,%16-19r,%0-3r%R"}, {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "UXTAH%c\t%8-11r,%16-19r,%0-3r%R"}, {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "SXTAB16%c\t%8-11r,%16-19r,%0-3r%R"}, {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "UXTAB16%c\t%8-11r, %16-19r,%0-3r%R"}, {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "SXTAB%c\t%8-11r,%16-19r,%0-3r%R"}, {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "UXTAB%c\t%8-11r,%16-19r,%0-3r%R"}, {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "BFC%c\t%8-11r,%E"}, {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "TST%c.W\t%16-19r,%S"}, {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "TEQ%c\t%16-19r,%S"}, {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "CMN%c.W\t%16-19r,%S"}, {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "CMP%c.W\t%16-19r,%S"}, {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "TST%c.W\t%16-19r,%M"}, {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "TEQ%c\t%16-19r,%M"}, {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "CMN%c.W\t%16-19r,%M"}, {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "CMP%c.W\t%16-19r,%M"}, {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "MOV%20'S%c.W\t%8-11r,%S"}, {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "MVN%20'S%c.W\t%8-11r,%S"}, {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "MLA%c\t%8-11r,%16-19r,%0-3r,%12-15r"}, {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "MLS%c\t%8-11r,%16-19r,%0-3r,%12-15r"}, {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "SMULL%c\t%12-15R,%8-11R,%16-19R,%0-3R"}, {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "UMULL%c\t%12-15R,%8-11R,%16-19R,%0-3R"}, {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "SMLAL%c\t%12-15R,%8-11R,%16-19R,%0-3R"}, {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "UMLAL%c\t%12-15R,%8-11R,%16-19R,%0-3R"}, {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "LDREX%c\t%12-15r,[%16-19r,#%0-7W]"}, {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "MOV%20's%c.W\t%8-11r,%M"}, {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "MVN%20'S%c.W\t%8-11r,%M"}, {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "PLD%c\t%a"}, {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "SBFX%c\t%8-11r,%16-19r,%F"}, {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "UBFX%c\t%8-11r,%16-19r,%F"}, {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "STR%wT%c\t%12-15r,%a"}, {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "BFI%c\t%8-11r,%16-19r,%E"}, {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "LDR%wT%c\t%12-15r,%a"}, {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "SSAT%c\t%8-11r,#%0-4d,%16-19r%s"}, {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "USAT%c\t%8-11r,#%0-4d,%16-19r%s"}, {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "ADR.W%c\t%8-11r,%16-19r,%I"}, // { ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I" }, {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "MOVW%c\t%8-11r, %J"}, {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "MOVT%c\t%8-11r,%J"}, {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "AND%20'S%c.W\t%8-11r,%16-19r,%S"}, {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "BIC%20'S%c.W\t%8-11r,%16-19r,%S"}, {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "ORR%20'S%c.W\t%8-11r,%16-19r,%S"}, {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "ORN%20'S%c\t%8-11r,%16-19r,%S"}, {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "EOR%20'S%c.W\t%8-11r,%16-19r,%S"}, {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "ADD%20'S%c.W\t%8-11r,%16-19r,%S"}, {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "ADC%20'S%c.W\t%8-11r,%16-19r,%S"}, {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "SBC%20'S%c.W\t%8-11r,%16-19r,%S"}, {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "SUB%20'S%c.W\t%8-11r,%16-19r,%S"}, {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "RSB%20'S%c.W\t%8-11r,%16-19r,%S"}, {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "STREX%c\t%8-11r,%12-15r,[%16-19r,#%0-7W]"}, {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "AND%20'S%c.W\t%8-11r,%16-19r,%M"}, {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "BIC%20'S%c.W\t%8-11r,%16-19r,%M"}, {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "ORR%20'S%c.W\t%8-11r,%16-19r,%M"}, {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "ORN%20'S%c\t%8-11r,%16-19r,%M"}, {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "EOR%20'S%c.W\t%8-11r,%16-19r,%M"}, {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "ADD%20'S%c.W\t%8-11r,%16-19r,%M"}, {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "ADC%20'S%c.W\t%8-11r,%16-19r,%M"}, {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "SBC%20'S%c.W\t%8-11r,%16-19r,%M"}, {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "SUB%20'S%c.W\t%8-11r,%16-19r,%M"}, {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "RSB%20'S%c.W\t%8-11r,%16-19r,%M"}, {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "STMIA%c.W\t%16-19r%21'!,%m"}, {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "LDMIA%c.W\t%16-19r%21'!,%m"}, {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "STMDB%c\t%16-19r%21'!,%m"}, {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "LDMDB%c\t%16-19r%21'!,%m"}, {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "STRD%c\t%12-15r,%8-11r,[%16-19r]"}, {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "LDRD%c\t%12-15r,%8-11r,[%16-19r]"}, {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "STRD%c\t%12-15r, %8-11r,[%16-19r, #%23`-%0-7W]%21'!%L"}, {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "LDRD%c\t%12-15r,%8-11r,[%16-19r,#%23`-%0-7W]%21'!%L"}, {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "STRD%c\t%12-15r, %8-11r,[%16-19r], #%23`-%0-7W%L"}, {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "LDRD%c\t%12-15r,%8-11r,[%16-19r],#%23`-%0-7W%L"}, {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "STR%w%c.W\t%12-15r,%a"}, {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "LDR%w%c.W\t%12-15r,%a"}, /* Filter out Bcc with cond=E or F, which are used for other instructions. */ {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "UNDEFINED (bcc, cond=0xF)"}, {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "UNDEFINED (bcc, cond=0xE)"}, {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "B%22-25c.w\t%b%X"}, {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "B%c.W\t%B%x"}, /* These have been 32-bit since the invention of Thumb. */ {ARM_EXT_V4T, 0xf000c000, 0xf800d001, "BLX%c\t%B%x"}, {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "BL%c\t%B%x"}, /* Fallback. */ {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, {0, 0, 0, 0} }; static const char *const arm_conditional[] = {"EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", "LE", "AL", "", ""}; static const char *const arm_fp_const[] = {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; static const char *const arm_shift[] = {"LSL", "LSR", "ASR", "ROR"}; typedef struct { const char *name; const char *description; const char *reg_names[16]; } arm_regname; static const arm_regname regnames[] = { { "raw" , "Select raw register names", { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, { "gcc", "Select register names used by GCC", { "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "R8", "R9", "R10", "R11", "R12", "SP", "LR", "PC" }}, //{ "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "R8", "R9", "sl", "fp", "ip", "SP", "LR", "PC" } }, { "std", "Select register names used in ARM's ISA documentation", { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, { "apcs", "Select register names used in the APCS", { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, { "atpcs", "Select register names used in the ATPCS", { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, { "special-atpcs", "Select special register names used in the ATPCS", { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, }; static const char *const iwmmxt_wwnames[] = {"b", "h", "w", "d"}; static const char *const iwmmxt_wwssnames[] = {"b", "bus", "bc", "bss", "h", "hus", "hc", "hss", "w", "wus", "wc", "wss", "d", "dus", "dc", "dss" }; static const char *const iwmmxt_regnames[] = { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" }; static const char *const iwmmxt_cregnames[] = { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" }; /* Default to GCC register name set. */ static unsigned int regname_selected = 1; #define NUM_ARM_REGNAMES NUM_ELEM (regnames) #define arm_regnames regnames[regname_selected].reg_names static bfd_boolean force_thumb = FALSE; /* Current IT instruction state. This contains the same state as the IT bits in the CPSR. */ static unsigned int ifthen_state; /* IT state for the next instruction. */ static unsigned int ifthen_next_state; /* The address of the insn for which the IT state is valid. */ //static bfd_vma ifthen_address; static unsigned int ifthen_address; #define IFTHEN_COND ((ifthen_state >> 4) & 0xf) /* Indicates that the current Conditional state is unconditional or outside an IT block. */ #define COND_UNCOND 16 /* Functions. */ int get_arm_regname_num_options (void) { return NUM_ARM_REGNAMES; } int set_arm_regname_option (int option) { int old = regname_selected; regname_selected = option; return old; } int get_arm_regnames (int option, const char **setname, const char **setdescription, const char *const **register_names) { *setname = regnames[option].name; *setdescription = regnames[option].description; *register_names = regnames[option].reg_names; return 16; } /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. Returns pointer to following character of the format string and fills in *VALUEP and *WIDTHP with the extracted value and number of bits extracted. WIDTHP can be NULL. */ static const char * arm_decode_bitfield (const char *ptr, unsigned long insn, unsigned long *valuep, int *widthp) { unsigned long value = 0; int width = 0; do { int start, end; int bits; for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) start = start * 10 + *ptr - '0'; if (*ptr == '-') for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) end = end * 10 + *ptr - '0'; else end = start; bits = end - start; if (bits < 0) restart (); value |= ((insn >> start) & ((2ul << bits) - 1)) << width; width += bits + 1; } while (*ptr++ == ','); *valuep = value; if (widthp) *widthp = width; return ptr - 1; } //static void //arm_decode_shift (long given, fprintf_ftype func, void *stream, // bfd_boolean print_shift) //{ // func ( "%s", arm_regnames[given & 0xf]); // // if ((given & 0xff0) != 0) // { // if ((given & 0x10) == 0) // { // int amount = (given & 0xf80) >> 7; // int shift = (given & 0x60) >> 5; // // if (amount == 0) // { // if (shift == 3) // { // func ( ", rrx"); // return; // } // // amount = 32; // } // // if (print_shift) // func ( ", %s #%d", arm_shift[shift], amount); // else // func ( ", #%d", amount); // } // else if ((given & 0x80) == 0x80) // func ( "\t; "); // else if (print_shift) // func ( ", %s %s", arm_shift[(given & 0x60) >> 5], // arm_regnames[(given & 0xf00) >> 8]); // else // func ( ", %s", arm_regnames[(given & 0xf00) >> 8]); // } //} #define W_BIT 21 #define I_BIT 22 #define U_BIT 23 #define P_BIT 24 #define WRITEBACK_BIT_SET (given & (1 << W_BIT)) #define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) #define PRE_BIT_SET (given & (1 << P_BIT)) /* Print one coprocessor instruction on INFO->STREAM. Return TRUE if the instuction matched, FALSE if this is not a recognised coprocessor instruction. */ static bfd_boolean print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, bfd_boolean thumb) { const struct opcode32 *insn; void *stream = 0; //info->stream; //fprintf_ftype func = info->fprintf_func; unsigned long mask; unsigned long value = 0; //struct arm_private_data *private_data = info->private_data; //unsigned long allowed_arches = private_data->features.coproc; int cond; for (insn = coprocessor_opcodes; insn->assembler; insn++) { unsigned long u_reg = 16; bfd_boolean is_unpredictable = FALSE; signed long value_in_comment = 0; const char *c; if (insn->arch == 0) switch (insn->value) { default: restart (); } mask = insn->mask; value = insn->value; if (thumb) { /* The high 4 bits are 0xe for Arm conditional instructions, and 0xe for arm unconditional instructions. The rest of the encoding is the same. */ mask |= 0xf0000000; value |= 0xe0000000; if (ifthen_state) cond = IFTHEN_COND; else cond = COND_UNCOND; } else { /* Only match unconditional instuctions against unconditional patterns. */ if ((given & 0xf0000000) == 0xf0000000) { mask |= 0xf0000000; cond = COND_UNCOND; } else { cond = (given >> 28) & 0xf; if (cond == 0xe) cond = COND_UNCOND; } } if ((given & mask) != value) continue; /* if ((insn->arch & allowed_arches) == 0) continue;*/ for (c = insn->assembler; *c; c++) { if (*c == '%') { switch (*++c) { case '%': func ("%%"); break; case 'A': { int rn = (given >> 16) & 0xf; bfd_vma offset = given & 0xff; func ("[%s", arm_regnames [(given >> 16) & 0xf]); if (PRE_BIT_SET || WRITEBACK_BIT_SET) { /* Not unindexed. The offset is scaled. */ offset = offset * 4; if (NEGATIVE_BIT_SET) offset = - offset; if (rn != 15) value_in_comment = offset; } if (PRE_BIT_SET) { if (offset) { func(",#%d]",(int)offset); if (WRITEBACK_BIT_SET) func("%s", "!"); } else if (NEGATIVE_BIT_SET) func (",#-0]"); else func ("]"); } else { func ("]"); if (WRITEBACK_BIT_SET) { if (offset) func (",#%d", (int) offset); else if (NEGATIVE_BIT_SET) func (",#-0"); } else { func (",{%s%d}", (NEGATIVE_BIT_SET && !offset) ? "-" : "", (int) offset); value_in_comment = offset; } } if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) { func ("\t; "); /* For unaligned PCs, apply off-by-alignment correction. */ //info->print_address_func print_address (offset + pc + 2 * 2 - (pc & 3)); } } break; case 'B': { int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); int offset = (given >> 1) & 0x3f; if (offset == 1) func ( "{D%d}", regno); else if (regno + offset > 32) func ( "{D%d-}", regno, regno + offset - 1); else { func( "{D%d-", regno); func( "D%d}", regno + offset - 1); } } break; case 'u': if (cond != COND_UNCOND) is_unpredictable = TRUE; /* Fall through. */ case 'c': func ( "%s", arm_conditional[cond]); break; case 'I': /* Print a Cirrus/DSP shift immediate. */ /* Immediates are 7bit signed ints with bits 0..3 in bits 0..3 of opcode and bits 4..6 in bits 5..7 of opcode. */ { int imm; imm = (given & 0xf) | ((given & 0xe0) >> 1); /* Is ``imm'' a negative number? */ if (imm & 0x40) imm |= (-1 & 0x3F); func ( "%d", imm); } break; case 'F': switch (given & 0x00408000) { case 0: func ( "4"); break; case 0x8000: func ( "1"); break; case 0x00400000: func ( "2"); break; default: func ( "3"); } break; case 'P': switch (given & 0x00080080) { case 0: func ( "S"); break; case 0x80: func ( "D"); break; case 0x00080000: func ( "E"); break; default: //func ( _("")); break; } break; case 'Q': switch (given & 0x00408000) { case 0: func ( "S"); break; case 0x8000: func ( "D"); break; case 0x00400000: func ( "E"); break; default: func ( "P"); break; } break; case 'R': switch (given & 0x60) { case 0: break; case 0x20: func ( "P"); break; case 0x40: func ( "M"); break; default: func ( "Z"); break; } break; case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { int width; c = arm_decode_bitfield (c, given, &value, &width); switch (*c) { case 'R': if (value == 15) is_unpredictable = TRUE; /* Fall through. */ case 'r': if (c[1] == 'u') { /* Eat the 'u' character. */ ++ c; if (u_reg == value) is_unpredictable = TRUE; u_reg = value; } func ( "%s", arm_regnames[value]); break; case 'D': func ( "D%ld", value); break; case 'Q': if (value & 1) func ( "", value >> 1); else func ( "Q%ld", value >> 1); break; case 'd': func ( "%ld", value); value_in_comment = value; break; case 'k': { int from = (given & (1 << 7)) ? 32 : 16; func ( "%ld", from - value); } break; case 'f': if (value > 7) func ( "#%s", arm_fp_const[value & 7]); else func ( "F%ld", value); break; case 'w': if (width == 2) func ( "%s", iwmmxt_wwnames[value]); else func ( "%s", iwmmxt_wwssnames[value]); break; case 'g': func ( "%s", iwmmxt_regnames[value]); break; case 'G': func ( "%s", iwmmxt_cregnames[value]); break; case 'x': func ( "0x%lx", (value & 0xffffffffUL)); break; case 'c': switch (value) { case 0: func ( "EQ"); break; case 1: func ( "VS"); break; case 2: func ( "GE"); break; case 3: func ( "GT"); break; default: func ( "??"); break; } break; case '`': c++; if (value == 0) func ( "%c", *c); break; case '\'': c++; if (value == ((1ul << width) - 1)) func ( "%c", *c); break; case '?': func ( "%c", c[(1 << width) - (int) value]); c += 1 << width; break; default: restart (); } break; case 'y': case 'z': { int single = *c++ == 'y'; int regno = 0; switch (*c) { case '4': /* Sm pair */ case '0': /* Sm, Dm */ regno = given & 0x0000000f; if (single) { regno <<= 1; regno += (given >> 5) & 1; } else regno += ((given >> 5) & 1) << 4; break; case '1': /* Sd, Dd */ regno = (given >> 12) & 0x0000000f; if (single) { regno <<= 1; regno += (given >> 22) & 1; } else regno += ((given >> 22) & 1) << 4; break; case '2': /* Sn, Dn */ regno = (given >> 16) & 0x0000000f; if (single) { regno <<= 1; regno += (given >> 7) & 1; } else regno += ((given >> 7) & 1) << 4; break; case '3': /* List */ func ( "{"); regno = (given >> 12) & 0x0000000f; if (single) { regno <<= 1; regno += (given >> 22) & 1; } else regno += ((given >> 22) & 1) << 4; break; default: restart (); } // func ( "%c%d", single ? 'S' : 'D', regno); if( single) func( "S"); else func( "D"); func( "%d", regno); if (*c == '3') { int count = given & 0xff; if (single == 0) count >>= 1; if (--count) { // func ( "-%c%d", // single ? 's' : 'd', //regno + count); if (single) func( "-S"); else func( "-D"); func( "%d", regno+count); } func ( "}"); } else if (*c == '4') { if (single) func( ",S"); else func( ",D"); func( "%d", regno + 1); // func( ", %c%d", single ? 's' : 'd', regno + 1); } } break; case 'L': switch (given & 0x00400100) { case 0x00000000: func ( "b"); break; case 0x00400000: func ( "h"); break; case 0x00000100: func ( "w"); break; case 0x00400100: func ( "d"); break; default: break; } break; case 'Z': { /* given (20, 23) | given (0, 3) */ value = ((given >> 16) & 0xf0) | (given & 0xf); func ( "%d", (int) value); } break; case 'l': /* This is like the 'A' operator, except that if the width field "M" is zero, then the offset is *not* multiplied by four. */ { int offset = given & 0xff; int multiplier = (given & 0x00000100) ? 4 : 1; func ( "[%s", arm_regnames [(given >> 16) & 0xf]); if (multiplier > 1) { value_in_comment = offset * multiplier; if (NEGATIVE_BIT_SET) value_in_comment = - value_in_comment; } if (offset) { if (PRE_BIT_SET) func ( ", #%s%d]%s", NEGATIVE_BIT_SET ? "-" : "", offset * multiplier, WRITEBACK_BIT_SET ? "!" : ""); else func ( "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", offset * multiplier); } else func ( "]"); } break; case 'r': { int imm4 = (given >> 4) & 0xf; int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); int ubit = ! NEGATIVE_BIT_SET; const char *rm = arm_regnames [given & 0xf]; const char *rn = arm_regnames [(given >> 16) & 0xf]; switch (puw_bits) { case 1: case 3: func ( "[%s],%c%s", rn, ubit ? '+' : '-', rm); if (imm4) func ( ",LSL #%d", imm4); break; case 4: case 5: case 6: case 7: func ( "[%s,%c%s", rn, ubit ? '+' : '-', rm); if (imm4 > 0) func ( ",LSL #%d", imm4); func ( "]"); if (puw_bits == 5 || puw_bits == 7) func ( "!"); break; default: func ( "INVALID"); } } break; case 'i': { long imm5; imm5 = ((given & 0x100) >> 4) | (given & 0xf); func ( "%ld", (imm5 == 0) ? 32 : imm5); } break; default: restart (); } } } else func ("%c", *c); } if (value_in_comment > 32 || value_in_comment < -16) func ("\t; 0x%lx", (value_in_comment & 0xffffffffUL)); if (is_unpredictable) func (UNPREDICTABLE_INSTRUCTION); return TRUE; } return FALSE; } /* Decodes and prints ARM addressing modes. Returns the offset used in the address, if any, if it is worthwhile printing the offset as a hexadecimal value in a comment at the end of the line of disassembly. */ //static signed long //print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) //{ // void *stream = info->stream; // //fprintf_ftype func = info->fprintf_func; // bfd_vma offset = 0; // // if (((given & 0x000f0000) == 0x000f0000) // && ((given & 0x02000000) == 0)) // { // offset = given & 0xfff; // // func ( "[pc"); // // if (PRE_BIT_SET) // { // /* Pre-indexed. Elide offset of positive zero when // non-writeback. */ // if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) // func ( ",#%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); // // if (NEGATIVE_BIT_SET) // offset = -offset; // // offset += pc + 8; // // /* Cope with the possibility of write-back // being used. Probably a very dangerous thing // for the programmer to do, but who are we to // argue ? */ // func ( "]%s", WRITEBACK_BIT_SET ? "!" : ""); // } // else /* Post indexed. */ // { // func ( "],#%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); // // /* Ie ignore the offset. */ // offset = pc + 8; // } // // func ( "\t; "); // //info->print_address_func (offset, info); // print_address (offset); // offset = 0; // } // else // { // func ( "[%s", // arm_regnames[(given >> 16) & 0xf]); // // if (PRE_BIT_SET) // { // if ((given & 0x02000000) == 0) // { // /* Elide offset of positive zero when non-writeback. */ // offset = given & 0xfff; // if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) // func ( ",#%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); // } // else // { // func ( ",%s", NEGATIVE_BIT_SET ? "-" : ""); // arm_decode_shift (given, func, stream, TRUE); // } // // func ( "]%s", // WRITEBACK_BIT_SET ? "!" : ""); // } // else // { // if ((given & 0x02000000) == 0) // { // /* Always show offset. */ // offset = given & 0xfff; // func ( "],#%s%d", // NEGATIVE_BIT_SET ? "-" : "", (int) offset); // } // else // { // func ( "],%s", // NEGATIVE_BIT_SET ? "-" : ""); // arm_decode_shift (given, func, stream, TRUE); // } // } // } // // return (signed long) offset; //} // /* Return the name of a v7A special register. */ static const char * banked_regname (unsigned reg) { switch (reg) { case 15: return "CPSR"; case 32: return "R8_usr"; case 33: return "R9_usr"; case 34: return "R10_usr"; case 35: return "R11_usr"; case 36: return "R12_usr"; case 37: return "SP_usr"; case 38: return "LR_usr"; case 40: return "R8_fiq"; case 41: return "R9_fiq"; case 42: return "R10_fiq"; case 43: return "R11_fiq"; case 44: return "R12_fiq"; case 45: return "SP_fiq"; case 46: return "LR_fiq"; case 48: return "LR_irq"; case 49: return "SP_irq"; case 50: return "LR_svc"; case 51: return "SP_svc"; case 52: return "LR_abt"; case 53: return "SP_abt"; case 54: return "LR_und"; case 55: return "SP_und"; case 60: return "LR_mon"; case 61: return "SP_mon"; case 62: return "ELR_hyp"; case 63: return "SP_hyp"; case 79: return "SPSR"; case 110: return "SPSR_fiq"; case 112: return "SPSR_irq"; case 114: return "SPSR_svc"; case 116: return "SPSR_abt"; case 118: return "SPSR_und"; case 124: return "SPSR_mon"; case 126: return "SPSR_hyp"; default: return NULL; } } /* Return the name of the DMB/DSB option. */ static const char * data_barrier_option (unsigned option) { switch (option & 0xf) { case 0xf: return "SY"; case 0xe: return "ST"; case 0xd: return "LD"; case 0xb: return "ISH"; case 0xa: return "ISHST"; case 0x9: return "ISHLD"; case 0x7: return "UN"; case 0x6: return "UNST"; case 0x5: return "NSHLD"; case 0x3: return "OSH"; case 0x2: return "OSHST"; case 0x1: return "OSHLD"; default: return NULL; } } /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ static void print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) { const struct opcode16 *insn; // void *stream = info->stream; int stream = 0; //fprintf_ftype func = info->fprintf_func; for (insn = thumb_opcodes; insn->assembler; insn++) if ((given & insn->mask) == insn->value) { signed long value_in_comment = 0; const char *c = insn->assembler; for (; *c; c++) { int domaskpc = 0; int domasklr = 0; if (*c != '%') { func ( "%c", *c); continue; } switch (*++c) { case '%': func ("%%"); break; case 'c': if (ifthen_state) func ("%s", arm_conditional[IFTHEN_COND]); break; case 'C': if (ifthen_state) func ("%s", arm_conditional[IFTHEN_COND]); else func ("S"); break; case 'I': { unsigned int tmp; ifthen_next_state = given & 0xff; for (tmp = given << 1; tmp & 0xf; tmp <<= 1) func (((given ^ tmp) & 0x10) ? "E" : "T"); func ("\t%s", arm_conditional[(given >> 4) & 0xf]); } break; case 'x': if (ifthen_next_state) func ("\t; unpredictable branch in IT block\n"); break; case 'X': if (ifthen_state) func ("\t; unpredictable ", arm_conditional[IFTHEN_COND]); break; case 'S': { long reg; reg = (given >> 3) & 0x7; if (given & (1 << 6)) reg += 8; func ("%s", arm_regnames[reg]); } break; case 'D': { long reg; reg = given & 0x7; if (given & (1 << 7)) reg += 8; func ("%s", arm_regnames[reg]); } break; case 'N': if (given & (1 << 8)) domasklr = 1; /* Fall through. */ case 'O': if (*c == 'O' && (given & (1 << 8))) domaskpc = 1; /* Fall through. */ case 'M': { int started = 0; int reg; func ("{"); /* It would be nice if we could spot ranges, and generate the rS-rE format: */ for (reg = 0; (reg < 8); reg++) if ((given & (1 << reg)) != 0) { if (started) func (","); started = 1; func ("%s", arm_regnames[reg]); } if (domasklr) { if (started) func (","); started = 1; func ("%s", arm_regnames[14] /* "lr" */); } if (domaskpc) { if (started) func (","); func ("%s", arm_regnames[15] /* "pc" */); } func ("}"); } break; case 'W': /* Print writeback indicator for a LDMIA. We are doing a writeback if the base register is not in the register mask. */ if ((given & (1 << ((given & 0x0700) >> 8))) == 0) func ("!"); break; case 'b': /* Print ARM V6T2 CZB address: pc+4+6 bits. */ { bfd_vma address = (pc + 4 + ((given & 0x00f8) >> 2) + ((given & 0x0200) >> 3)); //info->print_address_func (address, info); print_address (address); } break; case 's': /* Right shift immediate -- bits 6..10; 1-31 print as themselves, 0 prints as 32. */ { long imm = (given & 0x07c0) >> 6; if (imm == 0) imm = 32; func ("#%ld", imm); } break; case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { int bitstart = *c++ - '0'; int bitend = 0; while (*c >= '0' && *c <= '9') bitstart = (bitstart * 10) + *c++ - '0'; switch (*c) { case '-': { bfd_vma reg; c++; while (*c >= '0' && *c <= '9') bitend = (bitend * 10) + *c++ - '0'; if (!bitend) restart (); reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; switch (*c) { case 'r': func ("%s", arm_regnames[reg]); break; case 'd': func ("%ld", (long) reg); value_in_comment = reg; break; case 'H': func ("%ld", (long) (reg << 1)); value_in_comment = reg << 1; break; case 'W': func ("%ld", (long) (reg << 2)); value_in_comment = reg << 2; break; case 'a': /* PC-relative address -- the bottom two bits of the address are dropped before the calculation. */ //info->print_address_func print_address (((pc + 4) & ~3) + (reg << 2)); value_in_comment = 0; break; case 'x': func ("0x%04lx", (long) reg); break; case 'B': reg = ((reg ^ (1 << bitend)) - (1 << bitend)); //info->print_address_func (reg * 2 + pc + 4, info); print_address (reg * 2 + pc + 4); value_in_comment = 0; break; case 'c': func ("%s", arm_conditional [reg]); break; default: restart (); } } break; case '\'': c++; if ((given & (1 << bitstart)) != 0) func ("%c", *c); break; case '?': ++c; if ((given & (1 << bitstart)) != 0) func ("%c", *c++); else func ("%c", *++c); break; default: restart (); } } break; default: restart (); } } if (value_in_comment > 32 || value_in_comment < -16) func ("\t; 0x%lx", value_in_comment); return; } /* No match. */ restart (); } /* Return the name of an V7M special register. */ static const char * psr_name (int regno) { switch (regno) { case 0: return "APSR"; case 1: return "IAPSR"; case 2: return "EAPSR"; case 3: return "PSR"; case 5: return "IPSR"; case 6: return "EPSR"; case 7: return "IEPSR"; case 8: return "MSP"; case 9: return "PSP"; case 16: return "PRIMASK"; case 17: return "BASEPRI"; case 18: return "BASEPRI_MAX"; case 19: return "FAULTMASK"; case 20: return "CONTROL"; default: return ""; } } /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */ static void print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) { const struct opcode32 *insn; // void *stream = info->stream; //fprintf_ftype func = info->fprintf_func; int stream = 0; if (print_insn_coprocessor (pc, info, given, FALSE)) return; for (insn = thumb32_opcodes; insn->assembler; insn++) if ((given & insn->mask) == insn->value) { bfd_boolean is_unpredictable = FALSE; signed long value_in_comment = 0; const char *c = insn->assembler; for (; *c; c++) { if (*c != '%') { func ("%c", *c); continue; } switch (*++c) { case '%': func ("%%"); break; case 'c': if (ifthen_state) func ("%s", arm_conditional[IFTHEN_COND]); break; case 'x': if (ifthen_next_state) func ("\t; unpredictable branch in IT block\n"); break; case 'X': if (ifthen_state) func ("\t; unpredictable ", arm_conditional[IFTHEN_COND]); break; case 'I': { unsigned int imm12 = 0; imm12 |= (given & 0x000000ffu); imm12 |= (given & 0x00007000u) >> 4; imm12 |= (given & 0x04000000u) >> 15; func ("#%u", imm12); value_in_comment = imm12; } break; case 'M': { unsigned int bits = 0, imm, imm8, mod; bits |= (given & 0x000000ffu); bits |= (given & 0x00007000u) >> 4; bits |= (given & 0x04000000u) >> 15; imm8 = (bits & 0x0ff); mod = (bits & 0xf00) >> 8; switch (mod) { case 0: imm = imm8; break; case 1: imm = ((imm8 << 16) | imm8); break; case 2: imm = ((imm8 << 24) | (imm8 << 8)); break; case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break; default: mod = (bits & 0xf80) >> 7; imm8 = (bits & 0x07f) | 0x80; imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); } func ("#%u", imm); value_in_comment = imm; } break; case 'J': { unsigned int imm = 0; imm |= (given & 0x000000ffu); imm |= (given & 0x00007000u) >> 4; imm |= (given & 0x04000000u) >> 15; imm |= (given & 0x000f0000u) >> 4; func ("#%u", imm); value_in_comment = imm; } break; case 'K': { unsigned int imm = 0; imm |= (given & 0x000f0000u) >> 16; imm |= (given & 0x00000ff0u) >> 0; imm |= (given & 0x0000000fu) << 12; func ("#%u", imm); value_in_comment = imm; } break; case 'H': { unsigned int imm = 0; imm |= (given & 0x000f0000u) >> 4; imm |= (given & 0x00000fffu) >> 0; func ("#%u", imm); value_in_comment = imm; } break; case 'V': { unsigned int imm = 0; imm |= (given & 0x00000fffu); imm |= (given & 0x000f0000u) >> 4; func ("#%u", imm); value_in_comment = imm; } break; case 'S': { unsigned int reg = (given & 0x0000000fu); unsigned int stp = (given & 0x00000030u) >> 4; unsigned int imm = 0; imm |= (given & 0x000000c0u) >> 6; imm |= (given & 0x00007000u) >> 10; func ("%s", arm_regnames[reg]); switch (stp) { case 0: if (imm > 0) func (",LSL #%u", imm); break; case 1: if (imm == 0) imm = 32; func (",LSR #%u", imm); break; case 2: if (imm == 0) imm = 32; func (",ASR #%u", imm); break; case 3: if (imm == 0) func (",RRX"); else func (",ROR #%u", imm); } } break; case 'a': { unsigned int Rn = (given & 0x000f0000) >> 16; unsigned int U = ! NEGATIVE_BIT_SET; unsigned int op = (given & 0x00000f00) >> 8; unsigned int i12 = (given & 0x00000fff); unsigned int i8 = (given & 0x000000ff); bfd_boolean writeback = FALSE, postind = FALSE; bfd_vma offset = 0; func ("[%s", arm_regnames[Rn]); if (U) /* 12-bit positive immediate offset. */ { offset = i12; if (Rn != 15) value_in_comment = offset; } else if (Rn == 15) /* 12-bit negative immediate offset. */ offset = - (int) i12; else if (op == 0x0) /* Shifted register offset. */ { unsigned int Rm = (i8 & 0x0f); unsigned int sh = (i8 & 0x30) >> 4; func (",%s", arm_regnames[Rm]); if (sh) func (",LSL #%u", sh); func ("]"); break; } else switch (op) { case 0xE: /* 8-bit positive immediate offset. */ offset = i8; break; case 0xC: /* 8-bit negative immediate offset. */ offset = i8; offset = -offset; break; case 0xF: /* 8-bit + preindex with wb. */ offset = i8; writeback = TRUE; break; case 0xD: /* 8-bit - preindex with wb. */ offset = i8; offset = -offset; writeback = TRUE; break; case 0xB: /* 8-bit + postindex. */ offset = i8; postind = TRUE; break; case 0x9: /* 8-bit - postindex. */ offset = i8; offset = -offset; postind = TRUE; break; default: func (", ]"); goto skip; } if (postind) func ("],#%d", (int) offset); else { if (offset) func (",#%d", (int) offset); func (writeback ? "]!" : "]"); } if (Rn == 15) { func ("\t; "); //info->print_address_func (((pc + 4) & ~3) + offset, info); print_address (((pc + 4) & ~3) + offset); } } skip: break; case 'A': { unsigned int U = ! NEGATIVE_BIT_SET; unsigned int W = WRITEBACK_BIT_SET; unsigned int Rn = (given & 0x000f0000) >> 16; unsigned int off = (given & 0x000000ff); func ("[%s", arm_regnames[Rn]); if (PRE_BIT_SET) { if (off || !U) { func (", #%c%u", U ? '+' : '-', off * 4); value_in_comment = off * 4 * U ? 1 : -1; } func ("]"); if (W) func ("!"); } else { func ("], "); if (W) { func ("#%c%u", U ? '+' : '-', off * 4); value_in_comment = off * 4 * U ? 1 : -1; } else { func ("{%u}", off); value_in_comment = off; } } } break; case 'w': { unsigned int Sbit = (given & 0x01000000) >> 24; unsigned int type = (given & 0x00600000) >> 21; switch (type) { case 0: func (Sbit ? "SB" : "B"); break; case 1: func (Sbit ? "SH" : "H"); break; case 2: if (Sbit) func ("??"); break; case 3: func ("??"); break; } } break; case 'm': { int started = 0; int reg; func ("{"); for (reg = 0; reg < 16; reg++) if ((given & (1 << reg)) != 0) { if (started) func (","); started = 1; func ("%s", arm_regnames[reg]); } func ("}"); } break; case 'E': { char buf[16]; unsigned int msb = (given & 0x0000001f); unsigned int lsb = 0; lsb |= (given & 0x000000c0u) >> 6; lsb |= (given & 0x00007000u) >> 10; sprintf(buf, "#%u,#%u", lsb, msb - lsb + 1); func ("%s", buf ); } break; case 'F': { unsigned int width = (given & 0x0000001f) + 1; unsigned int lsb = 0; lsb |= (given & 0x000000c0u) >> 6; lsb |= (given & 0x00007000u) >> 10; func ("#%u,#%u", lsb, width); } break; case 'b': { unsigned int S = (given & 0x04000000u) >> 26; unsigned int J1 = (given & 0x00002000u) >> 13; unsigned int J2 = (given & 0x00000800u) >> 11; bfd_vma offset = 0; offset |= !S << 20; offset |= J2 << 19; offset |= J1 << 18; offset |= (given & 0x003f0000) >> 4; offset |= (given & 0x000007ff) << 1; offset -= (1 << 20); //info->print_address_func (pc + 4 + offset, info); print_address (pc + 4 + offset); } break; case 'B': { unsigned int S = (given & 0x04000000u) >> 26; unsigned int I1 = (given & 0x00002000u) >> 13; unsigned int I2 = (given & 0x00000800u) >> 11; bfd_vma offset = 0; offset |= !S << 24; offset |= !(I1 ^ S) << 23; offset |= !(I2 ^ S) << 22; offset |= (given & 0x03ff0000u) >> 4; offset |= (given & 0x000007ffu) << 1; offset -= (1 << 24); offset += pc + 4; /* BLX target addresses are always word aligned. */ if ((given & 0x00001000u) == 0) offset &= ~2u; //info->print_address_func (offset, info); print_address (offset); } break; case 's': { unsigned int shift = 0; shift |= (given & 0x000000c0u) >> 6; shift |= (given & 0x00007000u) >> 10; if (WRITEBACK_BIT_SET) func (",ASR #%u", shift); else if (shift) func (",LSL #%u", shift); /* else print nothing - lsl #0 */ } break; case 'R': { unsigned int rot = (given & 0x00000030) >> 4; if (rot) func (", ror #%u", rot * 8); } break; case 'U': if ((given & 0xf0) == 0x60) { switch (given & 0xf) { case 0xf: func ("SY"); break; default: func ("#%d", (int) given & 0xf); break; } } else { const char * opt = data_barrier_option (given & 0xf); if (opt != NULL) func ("%s", opt); else func ("#%d", (int) given & 0xf); } break; case 'C': if ((given & 0xff) == 0) { func ("%cPSR_", (given & 0x100000) ? 'S' : 'C'); if (given & 0x800) func ("f"); if (given & 0x400) func ("s"); if (given & 0x200) func ("x"); if (given & 0x100) func ("c"); } else if ((given & 0x20) == 0x20) { char const* name; unsigned sysm = (given & 0xf00) >> 8; sysm |= (given & 0x30); sysm |= (given & 0x00100000) >> 14; name = banked_regname (sysm); if (name != NULL) func ("%s", name); else func ("(UNDEF: %lu)", (unsigned long) sysm); } else { func ("%s", psr_name (given & 0xff)); } break; case 'D': if (((given & 0xff) == 0) || ((given & 0x20) == 0x20)) { char const* name; unsigned sm = (given & 0xf0000) >> 16; sm |= (given & 0x30); sm |= (given & 0x00100000) >> 14; name = banked_regname (sm); if (name != NULL) func ("%s", name); else func ("(UNDEF: %lu)", (unsigned long) sm); } else func ("%s", psr_name (given & 0xff)); break; case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { int width; unsigned long val; c = arm_decode_bitfield (c, given, &val, &width); switch (*c) { case 'd': func ("%lu", val); value_in_comment = val; break; case 'W': func ("%lu", val * 4); value_in_comment = val * 4; break; case 'S': if (val == 13) is_unpredictable = TRUE; /* Fall through. */ case 'R': if (val == 15) is_unpredictable = TRUE; /* Fall through. */ case 'r': func ("%s", arm_regnames[val]); break; case 'c': func ("%s", arm_conditional[val]); break; case '\'': c++; if (val == ((1ul << width) - 1)) func ("%c", *c); break; case '`': c++; if (val == 0) func ("%c", *c); break; case '?': func ("%c", c[(1 << width) - (int) val]); c += 1 << width; break; case 'x': func ("0x%lx", val & 0xffffffffUL); break; default: restart (); } } break; case 'L': /* PR binutils/12534 If we have a PC relative offset in an LDRD or STRD instructions then display the decoded address. */ if (((given >> 16) & 0xf) == 0xf) { bfd_vma offset = (given & 0xff) * 4; if ((given & (1 << 23)) == 0) offset = - offset; func ("\t@ "); print_address((pc & ~3) + 4 + offset); } break; default: restart (); } } if (value_in_comment > 32 || value_in_comment < -16) func ("\t; 0x%lx", value_in_comment); if (is_unpredictable) func (UNPREDICTABLE_INSTRUCTION); return; } /* No match. */ restart (); } /* Print data bytes on INFO->STREAM. */ static void print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, struct disassemble_info *info, long given) { switch (info->bytes_per_chunk) { case 1: info->fprintf_func (info->stream, ".byte\t0x%02lx", given); break; case 2: info->fprintf_func (info->stream, ".short\t0x%04lx", given); break; case 4: info->fprintf_func (info->stream, ".word\t0x%08lx", given); break; default: restart (); } } #if 0 /* Disallow mapping symbols ($a, $b, $d, $t etc) from being displayed in symbol relative addresses. */ bfd_boolean arm_symbol_is_valid (asymbol * sym, struct disassemble_info * info ATTRIBUTE_UNUSED) { const char * name; if (sym == NULL) return FALSE; name = bfd_asymbol_name (sym); return (name && *name != '$'); } #endif /* Parse an individual disassembler option. */ #if 0 void parse_arm_disassembler_option (char *option) { if (option == NULL) return; if (CONST_STRNEQ (option, "reg-names-")) { int i; option += 10; for (i = NUM_ARM_REGNAMES; i--;) if (strneq (option, regnames[i].name, strlen (regnames[i].name))) { regname_selected = i; break; } if (i < 0) /* XXX - should break 'option' at following delimiter. */ fprintf (stderr, _("Unrecognised register name set: %s\n"), option); } else if (CONST_STRNEQ (option, "force-thumb")) force_thumb = 1; else if (CONST_STRNEQ (option, "no-force-thumb")) force_thumb = 0; else /* XXX - should break 'option' at following delimiter. */ fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); return; } /* Parse the string of disassembler options, spliting it at whitespaces or commas. (Whitespace separators supported for backwards compatibility). */ static void parse_disassembler_options (char *options) { if (options == NULL) return; while (*options) { parse_arm_disassembler_option (options); /* Skip forward to next seperator. */ while ((*options) && (! ISSPACE (*options)) && (*options != ',')) ++ options; /* Skip forward past seperators. */ while (ISSPACE (*options) || (*options == ',')) ++ options; } } #endif /* Search back through the insn stream to determine if this instruction is conditionally executed. */ static void find_ifthen_state (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) { unsigned char b[2]; unsigned int insn; int status; /* COUNT is twice the number of instructions seen. It will be odd if we just crossed an instruction boundary. */ int count; int it_count; unsigned int seen_it; bfd_vma addr; ifthen_address = pc; ifthen_state = 0; addr = pc; count = 1; it_count = 0; seen_it = 0; /* Scan backwards looking for IT instructions, keeping track of where instruction boundaries are. We don't know if something is actually an IT instruction until we find a definite instruction boundary. */ for (;;) { // if (addr == 0 || info->symbol_at_address_func (addr, info)) if (addr == 0 ) { /* A symbol must be on an instruction boundary, and will not be within an IT block. */ if (seen_it && (count & 1)) break; return; } addr -= 2; //status = info->read_memory_func (addr, (bfd_byte *) b, 2, info); read_memory( (char *) addr , b, 2); if (little) insn = (b[0]) | (b[1] << 8); else insn = (b[1]) | (b[0] << 8); if (seen_it) { if ((insn & 0xf800) < 0xe800) { /* Addr + 2 is an instruction boundary. See if this matches the expected boundary based on the position of the last IT candidate. */ if (count & 1) break; seen_it = 0; } } if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) { /* This could be an IT instruction. */ seen_it = insn; it_count = count >> 1; } if ((insn & 0xf800) >= 0xe800) count++; else count = (count + 2) | 1; /* IT blocks contain at most 4 instructions. */ if (count >= 8 && !seen_it) return; } /* We found an IT instruction. */ #ifdef WITH_ITSTATE ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); if ((ifthen_state & 0xf) == 0) ifthen_state = 0; #endif } /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a mapping symbol. */ #if 0 static int is_mapping_symbol (struct disassemble_info *info, int n, enum map_type *map_type) { const char *name; name = bfd_asymbol_name (info->symtab[n]); if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') && (name[2] == 0 || name[2] == '.')) { *map_type = ((name[1] == 'a') ? MAP_ARM : (name[1] == 't') ? MAP_THUMB : MAP_DATA); return TRUE; } return FALSE; } /* Try to infer the code type (ARM or Thumb) from a mapping symbol. Returns nonzero if *MAP_TYPE was set. */ static int get_map_sym_type (struct disassemble_info *info, int n, enum map_type *map_type) { /* If the symbol is in a different section, ignore it. */ if (info->section != NULL && info->section != info->symtab[n]->section) return FALSE; return is_mapping_symbol (info, n, map_type); } /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol. Returns nonzero if *MAP_TYPE was set. */ static int get_sym_code_type (struct disassemble_info *info, int n, enum map_type *map_type) { elf_symbol_type *es; unsigned int type; /* If the symbol is in a different section, ignore it. */ if (info->section != NULL && info->section != info->symtab[n]->section) return FALSE; es = *(elf_symbol_type **)(info->symtab + n); type = ELF_ST_TYPE (es->internal_elf_sym.st_info); /* If the symbol has function type then use that. */ if (type == STT_FUNC || type == STT_GNU_IFUNC) { if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB) *map_type = MAP_THUMB; else *map_type = MAP_ARM; return TRUE; } return FALSE; } #endif /* Given a bfd_mach_arm_XXX value, this function fills in the fields of the supplied arm_feature_set structure with bitmasks indicating the support base architectures and coprocessor extensions. FIXME: This could more efficiently implemented as a constant array, although it would also be less robust. */ static void select_arm_features (unsigned long mach, arm_feature_set * features) { #undef ARM_FEATURE #define ARM_FEATURE(ARCH,CEXT) \ features->core = (ARCH); \ features->coproc = (CEXT) | FPU_FPA; \ return ARM_FEATURE (ARM_AEXT_V4T, 0) #if 0 switch (mach) { case bfd_mach_arm_2: ARM_ARCH_V2; case bfd_mach_arm_2a: ARM_ARCH_V2S; case bfd_mach_arm_3: ARM_ARCH_V3; case bfd_mach_arm_3M: ARM_ARCH_V3M; case bfd_mach_arm_4: ARM_ARCH_V4; case bfd_mach_arm_4T: ARM_ARCH_V4T; case bfd_mach_arm_5: ARM_ARCH_V5; case bfd_mach_arm_5T: ARM_ARCH_V5T; case bfd_mach_arm_5TE: ARM_ARCH_V5TE; case bfd_mach_arm_XScale: ARM_ARCH_XSCALE; case bfd_mach_arm_ep9312: ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK); case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT; case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2; /* If the machine type is unknown allow all architecture types and all extensions. */ case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL); default: restart (); } #endif } /* NOTE: There are no checks in these routines that the relevant number of data bytes exist. */ //int print_insn (vPlatform *vp, bfd_vma pc, struct disassemble_info *info, bfd_boolean little) static char *disabuff; static int pos; static void putbuf(char *s, int up) { while (*s) { if (*s == '\t') { disabuff[pos++] = ' '; /* at least one space */ while (pos % 8) { disabuff[pos++] = ' '; } } else { //if (up) // disabuff[pos++] = toupper(*s); //else disabuff[pos++] = *s; } s++; } } static void print_address(long addr) { char buf[64]; sprintf(buf, "0x%8.8X", addr); putbuf(buf, 0); } static void initfunc(char *buf) { disabuff = buf; pos = 0; } static void endfunc(void) { disabuff[pos] = 0; } static void func(const char* format, ...) { char buf[64]; va_list argList; va_start(argList, format); vsprintf(buf, format, argList); putbuf(buf, 0); va_end(argList); } //void func(const char *fmt, char *s) //{ // char buf[64]; // sprintf(buf, fmt, s); // putbuf(buf, 0); //} #ifndef DBG int print_insn(vPlatform *vp,uint32_t inpc, int start) { //unsigned char b[4]; long given; int status; int is_thumb = FALSE; int is_data = FALSE; int little_code = 0; struct disassemble_info *info = 0; /* dummy */ bfd_vma pc = inpc; unsigned int size = 4; void (*printer) (bfd_vma, struct disassemble_info *, long); bfd_boolean found = FALSE; //struct arm_private_data *private_data; uint16_t value; if (start) { /* prepare for new disssembly */ ifthen_state = 0; ifthen_next_state = 0; ifthen_address = 0; return 0; } is_thumb = TRUE; /* In Thumb mode we have the additional wrinkle of two instruction lengths. Fortunately, the bits that determine the length of the current instruction are always to be found in the first two bytes. */ printer = print_insn_thumb16; //info->bytes_per_chunk = 2; size = 2; //status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); //status = read_memory( pc , b, 2 ); status = read16( vp, pc, &value ); if (status<0) return -1; given = value; size = 2; /* These bit patterns signal a four-byte Thumb instruction. */ if ((given & 0xF800) == 0xF800 || (given & 0xF800) == 0xF000 || (given & 0xF800) == 0xE800) { status = read16( vp, pc+2, &value ); if (status<0) return -1; given = value | (given << 16); printer = print_insn_thumb32; size = 4; } #ifdef WITH_ITSTATE if (ifthen_address != pc) //find_ifthen_state (pc, info, little_code); find_ifthen_state (pc, info, 0); if (ifthen_state) { if ((ifthen_state & 0xf) == 0x8) ifthen_next_state = 0; else ifthen_next_state = (ifthen_state & 0xe0) | ((ifthen_state & 0xf) << 1); } #endif printer (pc, info, given); #ifdef WITH_ITSTATE ifthen_state = ifthen_next_state; ifthen_address += size; #endif return size; } #else /* DBG - debugger disassembler */ static int print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) { unsigned char b[4]; long given; // int status; int is_thumb = FALSE; int is_data = FALSE; int little_code = 0; unsigned int size = 4; void (*printer) (bfd_vma, struct disassemble_info *, long); bfd_boolean found = FALSE; struct arm_private_data *private_data; is_thumb = TRUE; printer = print_insn_thumb16; size = 2; // status = read_memory( pc , b, 2 ); read_memory( (char *) pc , b, 2 ); given = (b[1]) | (b[0] << 8); // if (!status) // { /* These bit patterns signal a four-byte Thumb instruction. */ if ((given & 0xF800) == 0xF800 || (given & 0xF800) == 0xF000 || (given & 0xF800) == 0xE800) { // status = read_memory( pc+2 , b, 2 ); read_memory( (char *) (pc+2) , b, 2 ); given = (b[1]) | (b[0] << 8) | (given << 16); printer = print_insn_thumb32; size = 4; } // } #ifdef WITH_ITSTATE if (ifthen_address != pc) find_ifthen_state (pc, info, 0); if (ifthen_state) { if ((ifthen_state & 0xf) == 0x8) ifthen_next_state = 0; else ifthen_next_state = (ifthen_state & 0xe0) | ((ifthen_state & 0xf) << 1); } #endif // if (status) // { // return -1; // } printer (pc, info, given); #ifdef WITH_ITSTATE if (is_thumb) { ifthen_state = ifthen_next_state; ifthen_address += size; } #endif return size; } static void read_memory( char * address , char *b, unsigned int size ) { int value; if( size == 2 ) { value = (unsigned int) *( (unsigned short *)address); b[0] = (value >> 8 ) & 0xFF; b[1] = value & 0xFF; } else if (size == 4 ) { value = (unsigned int) *( (unsigned short *)address); b[0] = (value >> 24 ) & 0xFF; b[1] = (value >> 16 ) & 0xFF; b[2] = (value >> 8 ) & 0xFF; b[3] = value & 0xFF; } else{ b[0] = b[1] = b[2] = b[3] = 0; } } int Instruction( unsigned long address, int doprint ) { int rv; char buf[64]; initfunc(buf); rv = print_insn (address, 0, FALSE); endfunc(); smallprintf(buf); return rv; } static char * last_daddr; void dasm( int argc, char ** argv) { // Forms // dasm // dasm PC // dasm ADDRESS // dasm ADDRESS INS int count,ins,value; unsigned char *address; char buf[64], b[8]; count = 16; if( argc == 3 ) { address = (unsigned char *) decval( argv[1] , 1 ); count = decval( argv[2] , 1 ); }else if( argc == 2 ) { if( !strcmpi( argv[1], "pc" ) ) { address = (unsigned char *) alregs.pc; } else address = (unsigned char *) decval( argv[1] , 1 ); }else if(argc == 1 ) { address = (unsigned char *) last_daddr; }else{ smallprintf("\n--Bad argument(s)"); return; } while( count ) { smallprintf("\n%X ",address); initfunc(buf); ins = print_insn ((int)address, 0, FALSE); endfunc(); switch ( ins ) { case 2: read_memory( address , b, 2 ); value = (b[1]) | (b[0] << 8); smallprintf("%x ",value); break; case 4: read_memory( address , b, 2 ); value = (b[1]) | (b[0] << 8); read_memory( address+2 , b, 2 ); value = (b[1]) | (b[0] << 8) | (value << 16); smallprintf("%X ",value); break; } smallprintf(buf); address += ins; count--; } last_daddr = address; } #endif