/* md407.h Register definitions */ #ifndef _MD407_H #define _MD407_H typedef unsigned char uint8_t; typedef unsigned short uint16_t; typedef unsigned long uint32_t; /*!< Peripheral memory map */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ //#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ //#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ //#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ //#define APB1PERIPH_BASE ((uint32_t)0x40000000) //#define APB2PERIPH_BASE ((uint32_t) 0x40010000) //#define AHB1PERIPH_BASE ((uint32_t) 0x40020000) //#define AHB2PERIPH_BASE ((uint32_t) 0x50000000) #define C_DEBUGEN 1 #define C_HALT (1<<1) #define C_STEP (1<<2) #define TRCENA (1<<24) #define MON_REQ (1<<19) #define MON_STEP (1<<18) #define MON_PEND (1<<17) #define MON_EN (1<<16) #define DWTTRAP (1<<2) #define BKPT (1<<1) #define HALTED 1 #define MMFAR ((unsigned long *) 0xE000ED34) #define BFAR ((unsigned long *) 0xE000ED38) #define FPU_CPACR ((volatile uint32_t *)0xE000ED88) #define FPU_FPCCR ((volatile uint32_t *)0xE000EF34) #define FPU_FPCAR ((volatile uint32_t *)0xE000EF38) #define FPU_FPDSCR ((volatile uint32_t *)0xE000EF3C) #define DBG_DHCSR ((volatile uint32_t *) 0xE000EDF0) #define DBG_DEMCR ((volatile uint32_t *) 0xE000EDFC) #define DBG_DFSR ((volatile uint32_t *) 0xE000ED30) /* ARM GPIO device */ typedef struct tagGpiodevice{ volatile uint32_t moder; /* 0x00 */ volatile uint32_t otyper; /* 0x04 */ volatile uint32_t ospeedr; /* 0x08 */ volatile uint32_t pupdr; /* 0x0C */ volatile uint32_t idr; /* 0x10 */ volatile uint32_t odr; /* 0x14 */ volatile uint16_t bsrl; /* 0x18 */ volatile uint16_t bsrh; /* 0x1C */ volatile uint32_t lckr; /* 0x20 */ volatile uint32_t afrl; /* 0x24 */ volatile uint32_t afrh; /* 0x28 */ } GPIO_DEVICE, *PGPIO_DEVICE; #define GPIOA ((PGPIO_DEVICE) 0x40020000) #define GPIOB ((PGPIO_DEVICE) 0x40020400) #define GPIOC ((PGPIO_DEVICE) 0x40020800) #define GPIOD ((PGPIO_DEVICE) 0x40020C00) #define GPIOE ((PGPIO_DEVICE) 0x40021000) /* RCC device */ typedef struct tagRccArmdevice { volatile uint32_t cr; /* 0x00 */ volatile uint32_t pllcfgr; /* 0x04 */ volatile uint32_t cfgr; /* 0x08 */ volatile uint32_t cir; /* 0x0C */ volatile uint32_t ahb1rstr; /* 0x10 */ volatile uint32_t ahb2rstr; /* 0x14 */ volatile uint32_t ahb3rstr; /* 0x18 */ volatile uint32_t reserved1; /* 0x1C */ volatile uint32_t apb1rstr; /* 0x20 */ volatile uint32_t apb2rstr; /* 0x24 */ volatile uint32_t reserved2; /* 0x28 */ volatile uint32_t reserved3; /* 0x2C */ volatile uint32_t ahb1enr; /* 0x30 */ volatile uint32_t ahb2enr; /* 0x34 */ volatile uint32_t ahb3enr; /* 0x38 */ volatile uint32_t reserved4; /* 0x3C */ volatile uint32_t apb1enr; /* 0x40 */ volatile uint32_t apb2enr; /* 0x44 */ volatile uint32_t reserved5; /* 0x48 */ volatile uint32_t reserved6; /* 0x4C */ volatile uint32_t ahb1lpenr; /* 0x50 */ volatile uint32_t ahb2lpenr; /* 0x54 */ volatile uint32_t ahb3lpenr; /* 0x58 */ volatile uint32_t reserved7; /* 0x5C */ volatile uint32_t apb1lpenr; /* 0x60 */ volatile uint32_t apb2lpenr; /* 0x64 */ volatile uint32_t reserved8; /* 0x68 */ volatile uint32_t reserved9; /* 0x6C */ volatile uint32_t bdcr; /* 0x70 */ volatile uint32_t csr; /* 0x74 */ volatile uint32_t reserved10; /* 0x78 */ volatile uint32_t reserved11; /* 0x7C */ volatile uint32_t sscgr; /* 0x80 */ volatile uint32_t plli2scfgr; /* 0x84 */ } RCC_ARM_DEVICE, *PRCC_ARM_DEVICE; #define RCC ((PRCC_ARM_DEVICE) 0x40023800) /* STM 407 USART, RM0090, page 1002*/ typedef struct tagUsartArmdevice{ volatile uint32_t sr; /* 0x00 */ volatile uint32_t dr; /* 0x04 */ volatile uint32_t brr; /* 0x08 */ volatile uint32_t cr1; /* 0x0C */ volatile uint32_t cr2; /* 0x10 */ volatile uint32_t cr3; /* 0x14 */ volatile uint32_t gtpr; /* 0x18 */ } USART_ARM_DEVICE, *PUSART_ARM_DEVICE; #define USART1 ((PUSART_ARM_DEVICE) 0x40011000) typedef struct tagSystickArmdevice{ volatile uint32_t ctrl; volatile uint32_t load; volatile uint32_t val; volatile uint32_t calib; } SYSTICK_ARM_DEVICE, *PSYSTICK_ARM_DEVICE; /* System Control block */ // volatile uint32_t actlr; #define SCB_ACTLR ((volatile unsigned long *)0xE000E008) typedef struct tagScbArmdevice{ volatile uint32_t cpuid; volatile uint32_t icsr; volatile uint32_t vtor; volatile uint32_t aircr; volatile uint32_t scr; volatile uint32_t ccr; volatile uint32_t shpr1; volatile uint32_t shpr2; volatile uint32_t shpr3; volatile uint32_t shcsr; volatile uint32_t cfsr; volatile uint32_t hfsr; volatile uint32_t dfsr; volatile uint32_t mmar; volatile uint32_t bfar; volatile uint32_t afsr; } SCB_ARM_DEVICE, *PSCB_ARM_DEVICE; #define SCB ((PSCB_ARM_DEVICE) 0xE000ED00) //#define SCB_VTOR (*(volatile unsigned long *)0xE000ED08) //#define SCB_AIRCR ((volatile unsigned long *)0xE000ED0C) //#define SCB_CCR (*(volatile unsigned long *)0xE000ED14) //#define SCB_SHCSR (*(volatile unsigned long *)0xE000ED24) //#define SCB_CFSR (*(volatile unsigned long *)0xE000ED28) //#define SCB_HFSR (*(volatile unsigned long *)0xE000ED2C) //#define SCB_DFSR (*(volatile unsigned long *)0xE000ED30) //#define SCB_SHPR1 (*(volatile unsigned long *)0xE000ED18) //#define SCB_SHPR2 (*(volatile unsigned long *)0xE000ED1C) //#define SCB_SHPR3 (*(volatile unsigned long *)0xE000ED20) /* Memory Protection Unit */ typedef struct tagMpuArmdevice{ volatile uint32_t typer; volatile uint32_t ctrl; volatile uint32_t rnr; volatile uint32_t rbar; volatile uint32_t rasr; volatile uint32_t rbar_a1; volatile uint32_t rasr_a1; volatile uint32_t rbar_a2; volatile uint32_t rasr_a2; } MPU_ARM_DEVICE, *PMPU_ARM_DEVICE; #define rbar_a3 rbar_a2 #define rasr_a3 rasr_a2 #define MPU ((PMPU_ARM_DEVICE) 0xE000ED90) /* System Configuration controller */ typedef struct tagSyscfgArmdevice{ volatile uint32_t memrm; volatile uint32_t pmc; volatile uint32_t exticr1; volatile uint32_t exticr2; volatile uint32_t exticr3; volatile uint32_t exticr4; volatile uint32_t cmpcr; } SYSCFG_ARM_DEVICE, *PSYSCFG_ARM_DEVICE; #define SYSCFG ((PSYSCFG_ARM_DEVICE) 0x40013800) /* EXTI */ typedef struct tagExtiArmdevice{ uint32_t imr; uint32_t emr; uint32_t rtsr; uint32_t ftsr; uint32_t swier; uint32_t pr; } EXTI_ARM_DEVICE, *PEXTI_ARM_DEVICE; #define EXTI ((PEXTI_ARM_DEVICE) 0x40013C00) /* NVIC device */ typedef struct tagNvicArmdevice{ uint32_t iser0; uint32_t iser1; uint32_t iser2; uint32_t icer0; uint32_t icer1; uint32_t icer2; uint32_t ispr0; uint32_t ispr1; uint32_t ispr2; uint32_t icpr0; uint32_t icpr1; uint32_t icpr2; uint32_t iabr0; uint32_t iabr1; uint32_t iabr2; uint32_t stir; uint8_t ipr[68]; } NVIC_ARM_DEVICE, *PNVIC_ARM_DEVICE; #define NVIC ((PNVIC_ARM_DEVICE) 0xE000E100) typedef struct tagPowerArmdevice { volatile uint32_t cr; volatile uint32_t csr; } POWER_ARM_DEVICE, *PPOWER_ARM_DEVICE; #define PWR ((PPOWER_ARM_DEVICE) (uint32_t)0x40007000) typedef struct tagFlashArmdevice { volatile uint32_t acr; volatile uint32_t keyr; volatile uint32_t optkeyr; volatile uint32_t sr; volatile uint32_t cr; volatile uint32_t optcr; volatile uint32_t optcr1; } FLASH_ARM_DEVICE, *PFLASH_ARM_DEVICE; #define FLASH ((PFLASH_ARM_DEVICE) (uint32_t) 0x40023C00) #define FLASH_ACR_ICEN ((uint32_t)0x00000200) #define FLASH_ACR_DCEN ((uint32_t)0x00000400) #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005) #define RCC_CR_HSEON ((uint32_t)0x00010000) #define RCC_CR_PLLON ((uint32_t)0x01000000) #define RCC_CR_PLLRDY ((uint32_t)0x02000000) #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000) #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */ #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */ typedef struct tagCAN_TxMailBox { volatile uint32_t TIR; /* CAN TX mailbox identifier register */ volatile uint32_t TDTR; /* CAN mailbox data length control and time stamp register */ volatile uint32_t TDLR; /* CAN mailbox data low register */ volatile uint32_t TDHR; /* CAN mailbox data high register */ } CAN_TxMailBox; typedef struct tagCAN_FIFOMailBox { volatile uint32_t RIR; /* CAN receive FIFO mailbox identifier register */ volatile uint32_t RDTR; /* CAN receive FIFO mailbox data length control and time stamp register */ volatile uint32_t RDLR; /* CAN receive FIFO mailbox data low register */ volatile uint32_t RDHR; /* CAN receive FIFO mailbox data high register */ } CAN_FIFOMailBox; typedef struct tagCAN_FilterRegister { volatile uint32_t FR1; /* CAN Filter bank register 1 */ volatile uint32_t FR2; /* CAN Filter bank register 1 */ } CAN_FilterRegister; typedef struct tagCAN_TypeDef { volatile uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ volatile uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ volatile uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ volatile uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ volatile uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ volatile uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ volatile uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ volatile uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ CAN_TxMailBox sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ CAN_FIFOMailBox sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ volatile uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ volatile uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ uint32_t RESERVED2; /*!< Reserved, 0x208 */ volatile uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ uint32_t RESERVED3; /*!< Reserved, 0x210 */ volatile uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ volatile uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ } CAN_TypeDef; #define CAN1_BASE 0x40006400 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) typedef struct tagDacArmdevice { volatile uint32_t cr; /*!< DAC control register, Address offset: 0x00 */ volatile uint32_t swtrigr; /*!< DAC software trigger register, Address offset: 0x04 */ volatile uint32_t dhr12r1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ volatile uint32_t dhr12l1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ volatile uint32_t dhr8r1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ volatile uint32_t dhr12r2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ volatile uint32_t dhr12l2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ volatile uint32_t dhr8r2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ volatile uint32_t dhr12rd; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ volatile uint32_t dhr12ld; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ volatile uint32_t dhr8rd; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ volatile uint32_t dor1; /*!< DAC channel1 data output register, Address offset: 0x2C */ volatile uint32_t dor2; /*!< DAC channel2 data output register, Address offset: 0x30 */ volatile uint32_t sr; /*!< DAC status register, Address offset: 0x34 */ } DAC_ARM_DEVICE, *PDAC_ARM_DEVICE; #define DAC_BASE 0x40007400 #define DAC ((PDAC_ARM_DEVICE) CAN1_BASE) #endif /* _MD407_H */