/*
	lu_control.h
	Register definitions for ST32F100
*/
#ifndef	_LU_CONTROL_H
#define _LU_CONTROL_H

typedef unsigned char 	uint8_t;
typedef unsigned short 	uint16_t;
typedef unsigned long 	uint32_t;

/*!< Peripheral memory map */
#ifdef NOLIB

typedef struct tagUsartDevice
{
	volatile unsigned short sr;
	volatile unsigned short Unused0;
	volatile unsigned short dr;
	volatile unsigned short Unused1;
	volatile unsigned short brr;
	volatile unsigned short Unused2;
	volatile unsigned short cr1;
	volatile unsigned short Unused3;
	volatile unsigned short cr2;
	volatile unsigned short Unused4;
	volatile unsigned short cr3;
	volatile unsigned short Unused5;
	volatile unsigned short gtpr;
} USART_DEVICE, *PUSART_DEVICE;

#define USART1  ((PUSART_DEVICE) 0x40011000)

#define	EN		(1<<13)
#define	TXEIE	(1<<7)
#define	TCIE	(1<<6)
#define	RXNEIE	(1<<5)
#define	TE		(1<<3)
#define	RE		(1<<2)

#define	TXE		(1<<7)	/* Transmit data register empty */
#define	RXNE	(1<<5)	/* Receive data register full */


/* ARM GPIO device */
typedef	struct	tagGpiodevice{
	volatile uint32_t	moder;	/* 0x00 */
	volatile uint32_t	otyper;	/* 0x04 */
	volatile uint32_t	ospeedr;	/* 0x08 */
	volatile uint32_t	pupdr;	/* 0x0C */
	volatile uint32_t	idr;	/* 0x10 */
	volatile uint32_t	odr;	/* 0x14 */
	volatile uint16_t	bsrl;	/* 0x18 */
	volatile uint16_t	bsrh;	/* 0x1C */
	volatile uint32_t	lckr;	/* 0x20 */
	volatile uint32_t	afrl;	/* 0x24 */
	volatile uint32_t	afrh;	/* 0x28 */
} GPIO_DEVICE, *PGPIO_DEVICE;


#define		GPIOA	((PGPIO_DEVICE) 0x40020000)
#define		GPIOB	((PGPIO_DEVICE) 0x40020400)
#define		GPIOC	((PGPIO_DEVICE) 0x40020800)
#define		GPIOD	((PGPIO_DEVICE) 0x40020C00)
#define		GPIOE	((PGPIO_DEVICE) 0x40021000)

/* RCC device */
typedef	struct	tagRccArmdevice {
	volatile uint32_t cr;		/* 0x00 */
	volatile uint32_t pllcfgr;	/* 0x04 */
	volatile uint32_t cfgr;	/* 0x08 */
	volatile uint32_t cir;	/* 0x0C */
	volatile uint32_t ahb1rstr;	/* 0x10 */
	volatile uint32_t ahb2rstr;	/* 0x14 */
	volatile uint32_t ahb3rstr;	/* 0x18 */
	volatile uint32_t reserved1; /* 0x1C */
	volatile uint32_t abp1rstr;	/* 0x20 */
	volatile uint32_t abp2rstr;	/* 0x24 */
	volatile uint32_t reserved2; /* 0x28 */
	volatile uint32_t reserved3; /* 0x2C */	
	volatile uint32_t ahb1enr;	/* 0x30 */
	volatile uint32_t ahb2enr;	/* 0x34 */
	volatile uint32_t ahb3enr;	/* 0x38 */
	volatile uint32_t reserved4; /* 0x3C */		
	volatile uint32_t apb1enr;	/* 0x40 */
	volatile uint32_t apb2enr;	/* 0x44 */
	volatile uint32_t reserved5; /* 0x48 */
	volatile uint32_t reserved6; /* 0x4C */	
	volatile uint32_t ahb1lpenr;	/* 0x50 */
	volatile uint32_t ahb2lpenr;	/* 0x54 */
	volatile uint32_t ahb3lpenr;	/* 0x58 */
	volatile uint32_t reserved7; /* 0x5C */	
	volatile uint32_t apb1lpenr;	/* 0x60 */
	volatile uint32_t apb2lpenr;	/* 0x64 */
	volatile uint32_t reserved8; /* 0x68 */
	volatile uint32_t reserved9; /* 0x6C */	
	volatile uint32_t bdcr;		/* 0x70 */
	volatile uint32_t csr;		/* 0x74 */
	volatile uint32_t reserved10; /* 0x78 */
	volatile uint32_t reserved11; /* 0x7C */	
	volatile uint32_t sscgr;		/* 0x80 */
	volatile uint32_t plli2scfgr;	/* 0x84 */
} RCC_ARM_DEVICE, *PRCC_ARM_DEVICE;

#define		RCC	((PRCC_ARM_DEVICE) 0x40023800)

/* STM 407 USART, RM0090, page 1002*/
typedef	struct	tagUsartArmdevice{
	volatile uint32_t sr;	/* 0x00 */
	volatile uint32_t dr;	/* 0x04 */
	volatile uint32_t brr;	/* 0x08 */
	volatile uint32_t cr1;	/* 0x0C */
	volatile uint32_t cr2;	/* 0x10 */
	volatile uint32_t cr3;	/* 0x14 */
	volatile uint32_t gtpr;	/* 0x18 */
} USART_ARM_DEVICE, *PUSART_ARM_DEVICE;

#define		USART1 	((PUSART_ARM_DEVICE) 0x40011000)


typedef	struct	tagSystickArmdevice{
	volatile uint32_t ctrl;
	volatile uint32_t load;
	volatile uint32_t val;
	volatile uint32_t calib;
} SYSTICK_ARM_DEVICE, *PSYSTICK_ARM_DEVICE;
#define	SYS_TICK	((PSYSTICK_ARM_DEVICE) (volatile uint32_t *)0xE000E010)

/* System Control block */

//	volatile uint32_t actlr;
#define	SCB_ACTLR	((volatile unsigned long *)0xE000E008)

typedef	struct	tagScbArmdevice{
	volatile uint32_t cpuid;
	volatile uint32_t icsr;
	volatile uint32_t vtor;
	volatile uint32_t aircr;
	volatile uint32_t scr;
	volatile uint32_t ccr;
	volatile uint32_t shpr1;
	volatile uint32_t shpr2;
	volatile uint32_t shpr3;
	volatile uint32_t shcsr;
	volatile uint32_t cfsr;
	volatile uint32_t hfsr;
	volatile uint32_t dfsr;
	volatile uint32_t mmar;
	volatile uint32_t bfar;
	volatile uint32_t afsr;

} SCB_ARM_DEVICE, *PSCB_ARM_DEVICE;


#define		SCB 	((PSCB_ARM_DEVICE) 0xE000ED00)

//#define SCB_VTOR (*(volatile unsigned long *)0xE000ED08)
//#define	SCB_AIRCR	((volatile unsigned long *)0xE000ED0C)
//#define SCB_CCR (*(volatile unsigned long *)0xE000ED14)
//#define SCB_SHCSR (*(volatile unsigned long *)0xE000ED24)
//#define SCB_CFSR (*(volatile unsigned long *)0xE000ED28)
//#define SCB_HFSR 	(*(volatile unsigned long *)0xE000ED2C)
//#define SCB_DFSR 	(*(volatile unsigned long *)0xE000ED30)

//#define SCB_SHPR1 (*(volatile unsigned long *)0xE000ED18)
//#define SCB_SHPR2 (*(volatile unsigned long *)0xE000ED1C)
//#define SCB_SHPR3 (*(volatile unsigned long *)0xE000ED20)


/* Memory Protection Unit */
typedef	struct	tagMpuArmdevice{
	volatile uint32_t typer;
	volatile uint32_t ctrl;
	volatile uint32_t rnr;
	volatile uint32_t rbar;
	volatile uint32_t rasr;
	volatile uint32_t rbar_a1;
	volatile uint32_t rasr_a1;
	volatile uint32_t rbar_a2;
	volatile uint32_t rasr_a2;
} MPU_ARM_DEVICE, *PMPU_ARM_DEVICE;
#define	rbar_a3	rbar_a2
#define	rasr_a3	rasr_a2

#define		MPU 	((PMPU_ARM_DEVICE) 0xE000ED90)


/* System Configuration controller */
typedef	struct	tagSyscfgArmdevice{
	volatile uint32_t memrm;
	volatile uint32_t pmc;
	volatile uint32_t exticr1;
	volatile uint32_t exticr2;
	volatile uint32_t exticr3;
	volatile uint32_t exticr4;
	volatile uint32_t cmpcr;
} SYSCFG_ARM_DEVICE, *PSYSCFG_ARM_DEVICE;

#define		SYSCFG 	((PSYSCFG_ARM_DEVICE) 0xE000ED00)


/* EXTI */
typedef	struct	tagExtiArmdevice{
	uint32_t imr;
	uint32_t emr;
	uint32_t rtsr;
	uint32_t ftsr;
	uint32_t swier;
	uint32_t pr;
} EXTI_ARM_DEVICE, *PEXTI_ARM_DEVICE;

/* NVIC device */
typedef	struct	tagNvicArmdevice{
	uint32_t iser0;
	uint32_t iser1;
	uint32_t iser2;
	uint32_t icer0;
	uint32_t icer1;
	uint32_t icer2;
	uint32_t ispr0;
	uint32_t ispr1;
	uint32_t ispr2;
	uint32_t icpr0;
	uint32_t icpr1;
	uint32_t icpr2;
	uint32_t iabr0;
	uint32_t iabr1;
	uint32_t iabr2;
	uint32_t stir;
	uint8_t		ipr[68];
} NVIC_ARM_DEVICE, *PNVIC_ARM_DEVICE;


typedef struct tagPowerArmdevice
{
  volatile uint32_t cr;  
  volatile uint32_t csr;  
} POWER_ARM_DEVICE, *PPOWER_ARM_DEVICE;

#define PWR	((PPOWER_ARM_DEVICE) (uint32_t)0x40007000)

typedef struct tagFlashArmdevice
{
  volatile uint32_t acr;
  volatile uint32_t keyr;
  volatile uint32_t optkeyr;
  volatile uint32_t sr;
  volatile uint32_t cr;
  volatile uint32_t optcr;
  volatile uint32_t optcr1;
} FLASH_ARM_DEVICE, *PFLASH_ARM_DEVICE;
         
#define FLASH	((PFLASH_ARM_DEVICE) (uint32_t) 0x40023C00)

#endif	/* NOLIB */


#endif 			/* _LU_CONTROL_H */