68HC11 Instructions

Mnenomic	Operation	Addressing  Mode	Instruction				Condition Codes
			Prebyte	Opcode	Operand	Cycles
ABA	Add Accumulators	INH	-	1B	-	2
ABX	Add B to X	INH	-	3A	-	3
ABY	Add B to Y	INH	18	3A	-	4
ADCA	Add with carry to A	IMM	-	89	ii	2
		DIR	-	99	dd	3
		EXT	-	B9	hh ll	4
		IND, X	-	A9	ff	4
		IND, Y	18	A9	ff	5
ADCB	Add with carry to B	IMM	-	C9	ii	2
		DIR	-	D9	dd	3
		EXT	-	F9	hh ll	4
		IND, X	-	E9	ff	4
		IND, Y	18	E9	ff	5
ADDA	Add memory to A	IMM	-	8B	ii	2
		DIR	-	9B	dd	3
		EXT	-	BB	hh ll	4
		IND, X	-	AB	ff	4
		IND, Y	18	AB	ff	5
ADDB	Add Memory to B	IMM	-	CB	ii	2
		DIR	-	DB	dd	3
		EXT	-	FB	hh ll	4
		IND, X	-	EB	ff	4
		IND, Y	18	EB	ff	5
ADDD	Add 16-bit to D	IMM	-	C3	jj kk	4
		DIR	-	D3	dd	5
		EXT	-	F3	hh ll	6
		IND, X	-	E3	ff	6
		IND, Y	18	E3	ff	7
ANDA	AND A with Memory	IMM	-	84	ii	2
		DIR	-	94	dd	3
		EXT	-	B4	hh ll	4
		IND, X	-	A4	ff	4
		IND, Y	18	A4	ff	5
ANDB	AND B with Memory	IMM	-	C4	ii	2
		DIR	-	D4	dd	3
		EXT	-	F4	hh ll	4
		IND, X	-	E4	ff	4
		IND, Y	18	E4	ff	5
ASL	Arithmetic Shift Left	EXT	-	78	hh ll	6
		IND, X	-	68	ff	6
		IND, Y	18	68	ff	7
ASLA	Arithmetic Shift Left A	INH	-	48	-	2
ASLB	Arithmetic Shift Left B	INH	-	58	-	2
ASLD	Arithmetic Shift Left D	INH	-	05	-	3
ASR	Arithmetic Shift Right	EXT	-	77	hh ll	6
		IND, X	-	67	ff	6
		IND, Y	18	67	ff	7
ASRA	Arithmetic Shift Right A	INH	-	47	-	2
ASRB	Arithmetic Shift Right B	INH	-	57	-	2
BCC	Branch if Carry Clear	REL	-	24	rr	3
BCLR	Clear Bit(s)	DIR	-	15	dd mm	6
		IND, X	-	1D	ff mm	7
		IND, Y	18	1D	ff	8
BCS	Branch if Carry Set	REL	-	25	rr	3
BEQ	Branch if = Zero	REL	-	27	rr	3
BGE	Branch if >= Zero	REL	-	2C	rr	3
BGT	Branch if > Zero	REL	-	2E	rr	3
BHI	Branch if Higher	REL	-	22	rr	3
BHS	Branch if Higher or Same	REL	-	24	rr	3
BITA	Bit(s) Test A with Memory	IMM	-	85	ii	2
		DIR	-	95	dd	3
		EXT	-	B5	hh ll	4
		IND, X	-	A5	ff	4
		IND, Y	18	A5	ff	5
BITB	Bit(s) Test B with Memory	IMM	-	C5	ii	2
		DIR	-	D5	dd	3
		EXT	-	F5	hh ll	4
		IND, X	-	E5	ff	4
		IND, Y	18	E5	ff	5
BLE	Branch if <= Zero	REL	-	2F	rr	3
BLO	Branch if Lower	REL	-	25	rr	3
BLS	Branch if Lower or Same	REL	-	23	rr	3
BLT	Branch if < Zero	REL	-	2D	rr	3
BMI	Branch if Minus	REL	-	2B	rr	3
BNE	Branch if not = Zero	REL	-	26	rr	3
BPL	Branch if Plus	REL	-	2A	rr	3
BRA	Branch Always	REL	-	20	rr	3
BRCLR	Branch if Bit(s) Clear	DIR	-	13	dd mm rr	6
		IND, X	-	1F	ff mm rr	7
		IND, Y	18	1F	ff mm rr	8
BRN	Branch Never	REL	-	21	rr	3
BRSET	Branch if Bit(s) Set	DIR	-	12	dd mm rr	6
		IND, X	-	1E	ff mm rr	7
		IND, Y	18	1E	ff mm rr	8
BSET	Set Bit(s)	DIR	-	14	dd mm rr	6
		IND, X	-	1C	ff mm rr	7
		IND, Y	18	1C	ff mm rr	8
BSR	Branch to Subroutine	REL	-	8D	rr	6
BVC	Branch if Overflow Clear	REL	-	28	rr	3
BVS	Branch if Overflow Set	REL	-	29	rr	3
Mnenomic	Operation	Addressing  Mode	Instruction				Condition Codes
			Prebyte	Opcode	Operand	Cycles
CBA	Compare A to B	INH	-	11	-	2
CLC	Clear Carry Bit	INH	-	0C	-	2
CLI	Clear Interrupt Mask	INH	-	0E	-	2
CLR	Clear Memory Byte	EXT	-	7F	hh ll	6
		IND, X	-	6F	ff	6
		IND, Y	18	6F	ff	7
CLRA	Clear Accumulator A	INH	-	4F	-	2
CLRB	Clear Accumulator B	INH	-	5F	-	2
CLV	Clear Overflow Flag	INH	-	0A	-	2
CMPA	Compare A to Memory	IMM	-	81	ii	2
		DIR	-	91	dd	3
		EXT	-	B1	hh ll	4
		IND, X	-	A1	ff	4
		IND, Y	18	A1	ff	5
CMPB	Compare B to Memory	IMM	-	C1	ii	2
		DIR	-	D1	dd	3
		EXT	-	F1	hh ll	4
		IND, X	-	E1	ff	4
		IND, Y	18	E1	ff	5
COM	Ones Complement Memory Byte	EXT	-	73	hh ll	6
		IND, X	-	63	ff	6
		IND, Y	18	63	ff	7
COMA	Ones Complement A	INH	-	43	-	2
COMB	Ones Complement B	INH	-	53	-	2
CPD	Compare D to Memory 16-Bit	IMM	1A	83	jj kk	5
		DIR	1A	93	dd	6
		EXT	1A	B3	hh ll	7
		IND, X	1A	A3	ff	7
		IND, Y	CD	A3	ff	7
CPX	Compare X to Memory 16-Bit	IMM	-	8C	jj kk	5
		DIR	-	9C	dd	6
		EXT	-	BC	hh ll	7
		IND, X	-	AC	ff	7
		IND, Y	-	AC	ff	7
CPY	Compare Y to Memory 16-Bit	IMM	18	8C	jj kk	5
		DIR	18	9C	dd	6
		EXT	18	BC	hh ll	7
		IND, X	1A	AC	ff	7
		IND, Y	18	AC	ff	7
DAA	Decimal Adjust A	INH	-	19	-	2
DEC	Decrement Memory Byte	EXT	-	7A	hh ll	6
		IND, X	-	6A	ff	6
		IND, Y	18	6A	ff	7
DECA	Decrement Accumulator A	INH	-	4A	-	2
DECB	Decrement Accumulator B	INH	-	5A	-	2
DES	Decrement Stack Pointer	INH	-	34	-	3
DEX	Decrement Index Register X	INH	-	09	-	3
DEY	Decrement Index Register Y	INH	-	09	-	4
EORA	Exclusive OR A with Memory	IMM	-	88	ii	2
		DIR	-	98	dd	3
		EXT	-	B8	hh ll	4
		IND, X	-	A8	ff	4
		IND, Y	18	A8	ff	5
EORB	Exclusive OR B with Memory	IMM	-	C8	ii	2
		DIR	-	D8	dd	3
		EXT	-	F8	hh ll	4
		IND, X	-	E8	ff	4
		IND, Y	18	E8	ff	5
FDIV	Fractional Divide 16 by 16	INH	-	03	-	41
IDIV	Integer Divide 16 by 16	INH	-	02	-	41
INC	Increment Memory Byte	EXT	-	7C	hh ll	6
		IND, X	-	6C	ff	6
		IND, Y	18	6C	ff	7
INCA	Increment Accumulator A	INH	-	4C	-	2
INCB	Increment Accumulator B	INH	-	5C	3	2
INS	Increment Stack Pointer	INH	-	31	-	3
INX	Increment Index Register X	INH	-	08	-	3
INY	Increment Index Register Y	INH	-	08	-	4
JMP	Jump	EXT	-	7E	hh ll	3
		IND, X	-	6E	ff	3
		IND, Y	18	6E	ff	4
JSR	Jump to Subroutine	DIR	-	9D	dd	5
		EXT	-	BD	hh ll	6
		IND, X	-	AD	ff	6
		IND, Y	18	AD	ff	7
Mnenomic	Operation	Addressing  Mode	Instruction				Condition Codes
			Prebyte	Opcode	Operand	Cycles
LDAA	Load Accumulator A	IMM	-	86	ii	2
		DIR	-	96	dd	3
		EXT	-	B6	hh ll	4
		IND, X	-	A6	ff	4
		IND, Y	18	A6	ff	5
LDAB	Load Accumulator B	IMM	-	C6	ii	2
		DIR	-	D6	dd	3
		EXT	-	F6	hh ll	4
		IND, X	-	E6	ff	4
		IND, Y	18	E6	ff	5
LDD	Load Double Accumulator D	IMM	-	CC	jj kk	3
		DIR	-	DC	dd	4
		EXT	-	FC	hh ll	5
		IND, X	-	EC	ff	5
		IND, Y	18	EC	ff	6
LDS	Load Stack Pointer	IMM	-	8E	jj kk	3
		DIR	-	9E	dd	4
		EXT	-	BE	hh ll	5
		IND, X	-	AE	ff	5
		IND, Y	18	AE	ff	6
LDX	Load Index Register X	IMM	-	CE	jj kk	3
		DIR	-	DE	dd	4
		EXT	-	FE	hh ll	5
		IND, X	-	EE	ff	5
		IND, Y	CD	EE	ff	6
LDY	Load Index Register Y	IMM	18	CE	jj kk	4
		DIR	18	DE	dd	5
		EXT	18	FE	hh ll	6
		IND, X	1A	EE	ff	6
		IND, Y	18	EE	ff	6
LSL	Logical Shift Left	EXT	-	78	hh ll	6
		IND, X	-	68	ff	6
		IND, Y	18	68	ff	7
LSLA	Logical Shift Left A	INH	-	48	-	2
LSLB	Logical Shift Left B	INH	-	58	-	2
LSLD	Logical Shift Left D	INH	-	05	-	3
LSR	Logical Shift Right	EXT	-	74	hh ll	6
		IND, X	-	64	ff	6
		IND, Y	18	64	ff	7
LSRA	Logical Shift Right A	INH	-	44	-	2
LSRB	Logical Shift Right B	INH	-	54	-	2
LSRD	Logical Shift Right D	INH	-	04	-	3
MUL	Multiply 8 by 8	INH	-	3D	-	10
NEG	Two`s Complement Memory Byte	EXT	-	70	hh ll	6
		IND, X	-	60	ff	6
		IND, Y	18	60	ff	7
NEGA	Two`s Complement A	INH	-	40	-	2
NEGB	Two`s Complement B	INH	-	50	-	2
NOP	No Operation	INH	-	01	-	2
ORAA	OR Accumulator A (Inclusive)	IMM	-	8A	ii	2
		DIR	-	9A	dd	3
		EXT	-	BA	hh ll	4
		IND, X	-	AA	ff	4
		IND, Y	18	AA	ff	5
ORAB	OR Accumulator B (Inclusive)	IMM	-	CA	ii	2
		DIR	-	DA	dd	3
		EXT	-	FA	hh ll	4
		IND, X	-	EA	ff	4
		IND, Y	18	EA	ff	5
PSHA	Push A onto Stack	INH	-	36	-	3
PSHB	Push B onto Stack	INH	-	37	-	3
PSHX	Push X onto Stack	INH	-	3C	-	4
PSHY	Push Y onto Stack	INH	18	3C	-	5
PULA	Pull A from Stack	INH	-	32	-	4
PULB	Pull B from Stack	INH	-	33	-	4
PULX	Pull X from Stack	INH	-	38	-	5
PULY	Pull Y from Stack	INH	18	38	-	6
ROL	Rotate Left	EXT	-	79	hh ll	6
		IND, X	-	69	ff	6
		IND, Y	18	69	ff	7
ROLA	Rotate Left A	INH	-	49	-	2
ROLB	Rotate Left B	INH	-	59	-	2
ROR	Rotate Right	EXT	-	76	hh ll	6
		IND, X	-	66	ff	6
		IND, Y	18	66	ff	7
RORA	Rotate Right A	INH	-	46	-	2
RORB	Rotate Right B	INH	-	56	-	2
RTI	Return from Interrupt	INH	-	3B	-	12
RTS	Return from Subroutine	INH	-	39	-	5
Mnenomic	Operation	Addressing  Mode	Instruction				Condition Codes
			Prebyte	Opcode	Operand	Cycles
SBA	Subtract B from A	INH	-	10	-	2
SBCA	Subtract with Carry from A	IMM	-	82	ii	2
		DIR	-	92	dd	3
		EXT	-	B2	hh ll	4
		IND, X	-	A2	ff	4
		IND, Y	18	A2	ff	5
SBCB	Subtract with Carry from B	IMM	-	C2	ii	2
		DIR	-	D2	dd	3
		EXT	-	F2	hh ll	4
		IND, X	-	E2	ff	4
		IND, Y	18	E2	ff	5
SEC	Set Carry	INH	-	0D	-	2
SEI	Set Interrupt Mask	INH	-	0F	-	2
SEV	Set Overflow Flag	INH	-	0B	-	2
STAA	Store Accumulator A	DIR	-	97	dd	3
		EXT	-	B7	hh ll	4
		IND, X	-	A7	ff	4
		IND, Y	18	A7	ff	5
STAB	Store Accumulator B	DIR	-	D7	dd	3
		EXT	-	F7	hh ll	4
		IND, X	-	E7	ff	4
		IND, Y	18	E7	ff	5
STD	Store Accumulator D	DIR	-	DD	dd	4
		EXT	-	FD	hh ll	5
		IND, X	-	ED	ff	5
		IND, Y	18	ED	ff	6
STOP	Stop Internal Clocks	INH	-	CF	-	2
STS	Store Stack Pointer	DIR	-	9F	dd	4
		EXT	-	BF	hh ll	5
		IND, X	-	AF	ff	5
		IND, Y	18	AF	ff	6
STX	Store Index Register X	DIR	-	DF	dd	4
		EXT	-	FF	hh ll	5
		IND, X	-	EF	ff	5
		IND, Y	18	EF	ff	6
STY	Store Index Register Y	DIR	18	DF	dd	5
		EXT	18	FF	hh ll	6
		IND, X	1A	EF	ff	6
		IND, Y	18	EF	ff	6
SUBA	Subtract Memory from A	IMM	-	80	ii	2
		DIR	-	90	dd	3
		EXT	-	B0	hh ll	4
		IND, X	-	A0	ff	4
		IND, Y	18	A0	ff	5
SUBB	Subtract Memory from B	IMM	-	C0	ii	2
		DIR	-	D0	dd	3
		EXT	-	F0	hh ll	4
		IND, X	-	E0	ff	4
		IND, Y	18	E0	ff	5
SUBD	Subtract Memory from D	IMM	-	83	ii	4
		DIR	-	93	dd	5
		EXT	-	B3	hh ll	6
		IND, X	-	A3	ff	6
		IND, Y	18	A3	ff	7
SWI	Software Interrupt	INH	-	3F	-	14
TAB	Transfer A to B	INH	-	16	-	2
TAP	Transfer A to CC Register	INH	-	06	-	2
TBA	Transfer B to A	INH	-	17	-	2
TEST	TEST (Only in Test Modes)	INH	-	00	-	*
TPA	Transfer CC Register to A	INH	-	07	-	2
TST	Test for Zero or Minus	EXT	-	7D	hh ll	6
		IND, X	-	6D	ff	6
		IND, Y	18	6D	ff	7
TSTA	Test A for Zero or Minus	INH	-	4D	-	2
TSTB	Test B for Zero or Minus	INH	-	5D	-	2
TSX	Transfer Stack Pointer to X	INH	-	30	-	3
TSY	Transfer Stack Pointer to Y	INH	18	30	-	4
TXS	Transfer X to Stack Pointer	INH	-	35	-	3
TYS	Transfer Y to Stack Pointer	INH	18	35	-	4
WAI	Wait for Interrupt	INH	-	3E	-	**
XGDX	Exchange D with X	INH	-	8F	-	3
XGDY	Exchange D with Y	INH	18	8F	-	4
Mnenomic	Operation	Addressing  Mode	Instruction				Condition Codes
			Prebyte	Opcode	Operand	Cycles

Cycle:

*    Infinity or until a RESET occurs.

**    12 cycles are used beginning with the opcode fetch.   A wait state is entered which remains in effect for an integer number of MPU E-clock cycles (n) until an interrupt is recognized.   Finally, two additional cycles are used to fetch the appropraite interrupt vector (14 + n total).

Operands:

dd    = 8-bit direct address ($0000-$00FF) (High byte assumed to be $00).

ff    = 8-bit positive offset $00 (0) to $FF (255) (Is added to index).

hh    = High-order byte of 16-bit extended address.

ii    = One byte of immediate data.

jj    = High-order byte of 16-bit immediate data.

kk    = Low-order byte of 16-bit immediate data.

ll    = Low-order byte of 16-bit extended address.

mm    = 8-bit mask (sets bits to be affected).

rr    = Signed relative offset $80 (-128) to $7F (+127)(Offset relative to address following machine code offset byte).