”Survey of commercial
risc processors, PART2: Detailed architectural survey”
Abstract
During the past years the aspects of computer architecture has undergone
rapid and revolutionary changes. Development of Reduced Instruction Set
Computer (RISC) architectures has introduced a number of new concepts in
computer architecture and design. This paper discuss RISC
design methodologies in general and focusing on RISC processors in embedded
Real-Time Systems. The report constitutes a part of the ESTEC ”RISC evaluation
study” performed by SAAB-SPACE (contract number 8686) during late 1990.