”Processor performance in real-time systems”
Abstract
During the last decade, RISC (Reduced Instruction Set Computer) processors, introduced mainly in work station applications, have brought excellent performance at low costs. In real time system design, the question arises; How do RISC processors comply to the specific demands of such a system?
This thesis describes seven RISC processors from an architectural point of view. Their ability to perform in a real-time system is elaborated and reported. Finally, real-time system hardware considerations are made from six different designs using three different processors. The system hardware considerations shows that in a real-time system design there is not very much to gain with a modern, general purpose RISC design such as SPARC. On the contrary, while the estimated performance for SPARC was just about the level of THOR, the board area became approximatly 40% larger, the power consumption 70% more and the expected failure became 45 % greater. This thesis is a revised version of two reports earlier published as a part of the ESTEC "RISC evaluation study ". performed by Saab Space (contract number 8686/89/NL/JG(SC)) during late 1990, namely: "Work Package 3: Survey of commercial RISC processors, Part 2: Detailed Architectural Survey" and "Work Package 4, Evaluation of processor configurations, part 1: Hardware Designs".

Keywords: Hard Real-Time Systems, RISC-architectures.