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Designing Correct Circuits 2006

25-26 March 2006, Vienna, Austria

A satellite event of the ETAPS 2006 group of conferences


Saturday, 25 March 2006
9:30-10:00 Zaher S. Andraus, Mark H. Liffiton, and Karem A. Sakallah (University of Michigan)
Microprocessor Verification Based on Datapath Abstraction and Refinement
10:00-10:30 Armin Biere (Johannes Kepler Universität)
Reachability Analysis with QBF
10:30-11:00 Coffee
11:00-11:30 Laurent Arditi, Gérard Berry, Marc Perreaut (Esterel Technologies), and Mike Kishinevsky (Intel)
An Implementation of Clock-Gating and Multi-Clocking in Esterel
11:30-12:00 Geoffrey Brown (Indiana University) and Lee Pike (Galois Connections)
"Easy" Parameterized Verification of Cross Clock-Domain Protocols
12:00-12:30 Joe Stoy (Bluespec Inc.)
Towards the Correct Design of Multiple Clock Domain Circuits
12:30-14:00 Lunch
14:00-14:30 Robert B. Jones and Noppanunt Utamaphethai (Intel)
Evolution and Impact of a Large Industrial Proof
14:30-15:00 Kathi Fisler (Worcester Polytechnic) and Shriram Krishnamurthi (Brown University)
Is Feature-Oriented Verification Useful for Hardware?
15:00-15:30 Koen Claessen (Chalmers)
A Coverage Analysis for Safety Property Lists
15:30-16:00 Coffee
16:00-16:30 Konrad Slind, Scott Owens (University of Utah), Juliano Iyoda, and Mike Gordon (University of Cambridge)
Proof producing synthesis of arithmetic and cryptographic hardware

Sunday, 26 March 2006
9:30-10:00 Sava Kristić, Mike Kishinevsky, and John O'Leary (Intel), and Jordi Cortadella (Universitat Politècnica de Catalunya)
Networks of Elastic Circuits
10:00-10:30 Sarah Thompson and Alan Mycroft (University of Cambridge)
Self-Healing Reconfigurable Manifolds
10:30-11:00 Coffee
11:30-12:00 Emil Axelsson, Koen Claessen, and Mary Sheeran (Chalmers)
Using Wired for Design Exploration
12:00-12:30 John T. O'Donnell (University of Glasgow)
Interconnect and Geometric Layout in Hydra
11:00-11:30 Tom Melham (Oxford University) and John O'Leary (Intel)
A Functional HDL for ReFLect
12:30-14:00 Lunch
14:00-14:30 Warren A. Hunt, Jr. and Erik Reeber (University of Texas at Austin)
Verification of Circuit Generators
14:30-15:00 Walid Taha (Rice University)
Two-level Languages and Circuit Design and Synthesis
15:00-15:30 Carl Seger (Intel)
The design of a floating point execution unit using the Integrated Design and Verification (IDV) system
15:30-16:00 Coffee
16:00-16:30 Panagiotis Manolios (Georgia Institute of Technology)
Automating the Verification of RTL-Level Pipelined Machines
16:30-17:00 Malay K. Ganai, Aarti Gupta, Akira Mukaiyama , and Kazutoshi Wakabayashi (NEC)
Another Dimension to High Level Synthesis: Verification
Evening Workshop Dinner

Last modified Sat Feb 11 17:41:14 GMT 2006