Designing Correct Circuits 2006 25-26 March 2006, Vienna, Austria A satellite event of the ETAPS 2006 group of conferences

Abstracts Accepted for Presentation at the Workshop

• Zaher S. Andraus, Mark H. Liffiton, and Karem A. Sakallah
  Microprocessor Verification Based on Datapath Abstraction and Refinement
• Laurent Arditi, Gérard Berry, Mike Kishinevsky, and Marc Perreaut
  An Implementation of Clock-Gating and Multi-Clocking in Esterel
• Emil Axelsson, Koen Claessen, and Mary Sheeran
  Using Wired for Design Exploration
• Armin Biere
  Reachability Analysis with QBF
• Geoffrey Brown and Lee Pike
  "Easy" Parameterized Verification of Cross Clock-Domain Protocols
• Koen Claessen
  A Coverage Analysis for Safety Property Lists
• Kathi Fisler and Shriram Krishnamurthi
  Is Feature-Oriented Verification Useful for Hardware?
• Malay K. Ganai, Aarti Gupta, Akira Mukaiyama , and Kazutoshi Wakabayashi
  Another Dimension to High Level Synthesis: Verification
• Warren A. Hunt, Jr. and Erik Reeber
  Verification of Circuit Generators
• Robert B. Jones and Noppanunt Utamaphethai
  Evolution and Impact of a Large Industrial Proof
• Sava Kristić, Jordi Cortadella, Mike Kishinevsky, and John O'Leary
  Networks of Elastic Circuits
• Panagiotis Manolios
  Automating the Verification of RTL-Level Pipelined Machines
• Tom Melham and John O'Leary
  A Functional HDL for ReFLect
• Jean Baptiste Note and Jean Vuillemin
  Towards Automatically Compiling Efficient FPGA Hardware
• John T. O'Donnell
  Interconnect and Geometric Layout in Hydra
• Carl Seger
  The design of a floating point execution unit using the Integrated Design and Verification (IDV) system
• Konrad Slind, Scott Owens, Juliano Iyoda, and Mike Gordon
  Proof producing synthesis of arithmetic and cryptographic hardware
• Joe Stoy
  Towards the Correct Design of Multiple Clock Domain Circuits
• Walid Taha
  Two-level Languages and Circuit Design and Synthesis
• Sarah Thompson and Alan Mycroft
  Self-Healing Reconfigurable Manifolds