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Book Chapters

  • B. Goel, S.A. McKee, M. Själander, “Techniques to Measure, Model, and Manage Power”, Elsevier Advances in Computers, vol. 87, Green Computing, November 2012, pp. 7-54.
  • S. Wong, L. Carro, M. Rutzig, M.M. Matos, R. Giorgi, N. Puzovic, S. Kaxiras, M. Cintra, G. Desoli, P. Gai, S.A. McKee, A. Zaks, “ERA — Embedded Reconfigurable Architectures”, Reconfigurable Computing: From FPGAs to Hardware/Software Co-design, J.M.P. Cardoso, M. Hübner, Eds., Springer, July 2011, pp. 239-259.
  • S.A. McKee, R.W. Wisniewski, “The Memory Wall”, Encyclopedia of Parallel Computing, D. Padua, Ed., Springer, 2011, pp. 1110-1116.


Refereed Conferences

Refereed Workshops

  • O. Jeppsson, S.A. McKee, “Towards a Scalable Functional Simulator for the Adapteva Epiphany Architecture”, Workshop on Programmability for Multicores (MULTIPROG), January 2015.
  • O. Jeppsson, S.A. McKee, “Simulating a Manycore Processor: A Scalable Functional Model for the Adapteva Epiphany Architecture”, Swedish Workshop on Multi-Core Computing (MCC), November 2014.
  • J. Lidman, S.A. McKee, D. Quinlan, C. Liao, “An Automated Performance-Aware Approach to Reliability Transformations”, Workshop on Resiliency in High Performance Computing with Clouds, Grids, and Clusters (Resilience), August 2014.
  • D. Knyaginin, S.A. McKee, G.N. Gaydadjiev, “A Hybrid Main Memory Systems Taxonomy”, Memory Architecture and Organization Workshop, October 2012.
  • J. Lidman, D. Quinlan., C. Liao, S.A. McKee, “ROSE::FTTransform — A Source-to-Source Transformation Framework for ExaScale Fault-Tolerance Research”, Workshop on Fault Tolerance for HPC at Extreme Scale (FTXS), June 2012.
  • G. Goumas, S.A. McKee, M Själander, T.R. Gross, S. Karlsson, C.W. Probst, L. Zhang, “Adapt or Become Extinct!: the Case for a Unified Framework for Deployment-Time Optimization”, Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era (EXADAPT), June 2011, pp. 46-51.
  • M. Andersson, L. Svensson, M. Själander, S.A. McKee, E. Catovic, P. Ingelha, “Yield Optimization Using Redundant Cores”, Swedish Workshop on Multi-Core Computing (MCC), pp. 30-33, October 2010.
  • M. Zahran, S.A. McKee, “Adaptive Block Placement Policy for Cache Hierarchies”, Workshop on Statistical and Machine Learning Approaches to Architecture and Compilation (SMART), January 2009.
  • K. Singh, M. Bhadauria, S.A. McKee, “Real Time Power Estimation and Thread Scheduling via Performance Counters”, Workshop on Design, Architecture, and Simulation of Chip-Multiprocessors (dasCMP), November 2008. Computer Architecture News, 37(2):46-55, May 2009.
  • M. Zahran, S.A. McKee, “Enterprise-Like Cache Hierarchy Management in the Manycore Era”, Workshop on Memory System Performance and Correctness (MSPC), March 2008.
  • P.A. Castillo, A.M. Mora, J. J. Merelo Guervós, J.L. Jiménez Laredo, M. Moretó, F.J. Cazorla, M. Valero, S.A. McKee, “Architecture Performance Prediction Using Evolutionary Artificial Neural Networks”, EvoWorkshops, March 2008, pp. 175-183.
  • V.M. Weaver, S.A. McKee, “Are Cycle Accurate Simulations a Waste of Time?”, Workshop on Duplicating, Deconstructing, and Debunking, June 2008.
  • M. Curtis-Maury, K. Singh, S.A. McKee, F. Blagojevic, D.S. Nikolopoulos, B.R. de Supinski, M. Schulz, “Identifying Energy-Efficient Concurrency Levels Using Machine Learning”, International Green Workshop, IEEE International Conference on Cluster Computing, September 2007, pp. 488-495.
  • E. Ipek, J.F. Martínez, B.R. de Supinski, S.A. McKee, M. Schulz, “Dynamic Program Phase Detection in Distributed Shared-Memory Multiprocessors”, Workshop on the National Science Foundation Next Generation Software Program (NSF/NGS), April 2006, p. 280.
  • M. Schulz, B.S. White, S.A. McKee, H.S. Lee, “A Vision for Next-Generation System Monitoring”, Workshop on Hardware Performance Monitor Design and Functionality, February 2005, pp. 65-74.
  • T. Suh, H.S. Lee, S.A. McKee, M. Schulz, “Evaluating System-Wide Monitoring Capsule Design Using Xilinx Virtex-II Pro FPGA”, Workshop on Architecture Research using FPGA Platforms (WARFP), February 2005 (abstract and presentation).
  • P.K. Szwed, D. Marques, R.M. Buels, S.A. McKee, M. Schulz, “SimSnap: Fast-Forwarding via Native Execution and Application-Level Checkpointing”, Workshop on the Interaction between Compilers and Computer Architectures (Interact), February 2004.
  • Z. Fang, S.A. McKee, “MPEG4: Fallacies and Paradoxes”, IEEE Workshop on Workload Characterization (WWC), November 2002, pp. 91-97.
  • T. Mohan, B.R. de Supinski, S.A. McKee, F. Mueller, A. Yoo, “Dynamic Detection of Streams in Memory References”, Annual Symposium of the Los Alamos Computer Science Institute (LACSI), October 2001 (abstract and poster).
  • B.R. de Supinski, A. Yoo, F. Mueller, S.A. McKee, “Benchmarking SMP Memory Systems Performance”, SCICOMP (IBM SP Scientific Computing User Group), October 2001 (abstract and presentation).
  • F. Mueller, T. Mohan, B.R. de Supinski, S.A. McKee, A. Yoo, “Partial Data Traces: Efficient Generation and Representation”, Workshop on Binary Translation (WBT), September 2001.
  • L. Zhang, S.A. McKee, J.B. Carter, W.C. Hsieh, “Prefetching within the Impulse Adaptable Memory Controller: Initial Results”, Workshop on Solving the Memory Wall Problem, June 2000.
  • S.A. McKee, “Compiling for Efficient Memory Utilization”, Workshop on the Interaction of Compilers and Computer Architecture (INTERACT), February 1996 (abstract and presentation).

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