Embedded and Networked Processors

Embedded and Networked Processors focuses on research problems related to the design of digital devices and wireless networks for embedded systems. Specific attention is currently given to :

1. RFID (Radio Frequency IDentification) systems. With current focus on energy-efficient RFID wireless network data communication protocols.

2. Design and implementation of arithmetic components for digital signal processing units using non-standard number systems like RNS (Residue Number System) and SD (Signed Digit).

Group members

• Lars Bengtsson, PhD, Docent, Associate Professor.
• Björn Nilsson, Lic Eng, Industry PhD student, working on RFID.

Graduated PhD students:

• Björn Nilsson, PhD degree, thesis: "Energy Efficient Protocols for Active RFID”, defence: June 2, 2010.
• Do Quang Minh, PhD degree, thesis: "Accurate Leakage-Conscious Architecture-level Power Estimation for SRAM-based Memory Structures", defence: June 18, 2007.
• Do Quang Minh, Lic degree, thesis: "Towards a Power and Performance Simulation Framework for Parallel DSP Architectures",  2005.
• Björn Nilsson, lic degree, thesis: "Towards Energy Efficient Protocols for Active RFID", Nov 23, 2007.

Graduated MSc students (doing their thesis at Chalmers within the research group):

· Amin Roostaei and Maziyar Namini: Thesis: “ Implementation of the Digital Control Block in a Low-Power, Low-Cost RFID Tag”

· Björn Felber and Shine Vallath Sadhanandan:  Thesis: "Implementation of an RFID-reader based on the EGON protocol".

• Jacob Stille, Thesis: "Implementation of an 8x8 2D IDCT Using RNS/SD".
• Andreas Persson, Thesis: "A Comparative Study of Moduli Sets for Signed-Digit Residue Number Systems".
• Firas Milh. Thesis: "Implementation of the DSP-PP Cycle-True Simulator Using SystemC".
• Joachim Mårtensson: Thesis: "An Instruction Scheduler and Power Dissipation Estimation Framework for the ManArray DSP"
• Anders Lindström and Michael Nordseth. Thesis: "Design Space Exploration of Binary Arithmetic Circuits and Design of Circuits for Alternative Arithmetic Systems".
• Andreas Lindahl: Thesis: "A Comparative Study of FIR Filter Implementations using RNS/SD vs. 2's-complement Representation".
• Björn Liljeqvist. Thesis: "Visions and Facts - A Survey of Network Processors".
• Lars-Olle Arnesson. Thesis: "Emulation of a Wire speed GRID Architecture".
• Niklas Therning: Thesis: "Jalapeno – Decentralized Grid Computing using Peer-to-Peer Technology".

Current Research Areas:

• Active RFID systems.
• DSP hardware blocks using RNS and SD number representations.

Projects:

• Active RFID. Financed by the KK-foundation. Industrial PhD student from Free2Move AB, Halmstad, Sweden.
• Circuits using non-standard arithmetic (Redundant Number System and Signed Digit)  in digital signal processing hardware. An on-line VHDL library is available at www.ce.chalmers.se/arithdb.

Past Research:

• High-performance flexible SIMD processors for signal processing in embedded systems.
• Multiple antenna, phase controlled, doppler radar signal processing (AESA antennas - Space-Time Adaptive Processing - STAP) using processor arrays in VLSI and FPGA technology.
• Neural network digital hardware using SIMD processor arrays.
• The "DSP-PP" project: Aimed at developing a software architecture-level power estimation tool for parallel DSP architectures capable of estimating the power (dynamic as well as static) consumption in the early stage of a parallel DSP architecture development.
  

Publications:

"An Energy and Application Scenario Aware Active RFID Protocol”, B. Nilsson, L. Bengtsson, B. Svensson, EURASIP Journal on Wireless Communications and Networking, vol. 2010, Article ID 432938, 15 pp., 2010. doi:10.1155/2010/432938.

“A Snoozing Frequency Binary Tree Protocol”, B. Nilsson, L. Bengtsson, B. Svensson, The Third International EURASIP Workshop on RFID Technology, 6-7 September 2010, La Manga del Mar Menor, Cartagena, Spain.

“An Active Backscatter Wake-up and Tag Identification Extraction Protocol for Low Cost and Low Power RFID ”, B. Nilsson, L. Bengtsson, B. Svensson, P-A. Wiberg, U. Bilstrup. Proceedings of RFID-TA2010, IEEE Conference on RFID - Technology and Applications, June 17-19, 2010, Guangzhou, China, pp. 86-91.

“A Low Power-Long Range Active RFID-system Consisting of Active Backscatter Transponders”, E. Nilsson, B. Nilsson, L. Bengtsson, B. Svensson, P-A. Wiberg, U. Bilstrup. Proceedings of RFID-TA2010, IEEE Conference on RFID - Technology and Applications, June 17-19, 2010, Guangzhou, China, pp. 26-30.

"An Application Dependent  Medium Access Protocol for Active RFID Using Dynamic Tuning of the Back-off Algorithm", B. Nilsson, L. Bengtsson, B. Svensson,  Proceedings of the 2009 IEEE Conference on RFID, Orlando, Florida, April 27-28, 2009, pp. 72-79.

"Forward and Reverse Converters and Moduli Set Selection in Signed-Digit Residue Number Systems", A. Persson and L. Bengtsson,  Springer Journal of Signal Processing Systems (fm. Journal of VLSI Signal Processing Systems),  Volume 56, Issue 1, July 2009, pp. 1-15, DOI: 10.1007/s11265-008-0249-8.

"Selecting Back-Off Algorithm in Active RFID CSMA/CA Based Medium-Access Protocols", Björn Nilsson, Lars Bengtsson, and Bertil Svensson, IEEE Symposium on Industrial Embedded Systems - SIES'2008, Montpellier, France, 11-13 June, 2008.

"Protocols for Active RFID - The Energy Consumption Aspect", Björn Nilsson, Lars Bengtsson, Per-Arne Wiberg, and Bertil Svensson,  IEEE Second  Symposium on Industrial Embedded Systems - SIES'2007, Lisbon, Portugal, 4-6 July, 2007, pp- 41-48.

"Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays", Minh Q. Do, Mindaugas Drazdziulis, Per Larsson-Edefors, and Lars Bengtsson, 8^th International Symposium on Quality Electronic Design (ISQED’07), San Jose, CA, USA, March 26-28, 2007.

"Towards an Energy Efficient Protocol for Active RFID",  Björn Nilsson, Lars Bengtsson, Urban Bilstrup, Per-Arne Wiberg, and Bertil Svensson, IEEE Symposium on Industrial Embedded Systems - IES'2006, Antibe, France, 18-20 Oct., pp. 1-4.

"Reverse Converter Architectures for Signed-Digit Residue Systems", A. Persson and L. Bengtsson, IEEE International Conference on Circuits and Systems, Kos, Greece,  May 21-25, 2006. 4 pp.

"The REMAP Reconfigurable Architecture: a Retrospective", L. Bengtsson, A. Linde, T. Nordström, B. Svensson., M. Taveniku, Chapter in "FPGA Implementations of Neural Networks", eds. Omondi & Rajapakse, Springer-Verlag, ISBN: 0-387-28485-0.

“Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration”, Minh Do, Mindaugas, P. Larsson-Edefors, L. Bengtsson, Proceedings of ISQED’06: 7’th IEEE International Sy,posium on Quality Electronics Design, 27-29 March, San Jose, USA.

"A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation", Andreas Lindahl and Lars Bengtsson, Proceedings of 8'th EUROMICRO Conference on Digital  System Design (DSD'05), Porto, Portugal, August 30th - September 3rd, 2005, IEEE Computer Society Press, pp. 42-47.

"Jalapeno - Decentralized Grid Computing using Peer-to-Peer Technology", N. Therning and L. Bengtsson, 2005 ACM International Conference on Computing Frontiers, pp. 59-65, May 4-6, Ischia, Italy.

"Table-Based Total Power Consumption Estimation of Memory Arrays for Architects", Minh Q. Do, Per Larsson-Edefors and Lars Bengtsson, Lecture Notes in  Computer Science (LNCS) vol 3254, pp. 869-878X, Springer Verlag, 14'th Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Santorini, Greece, September 15-17, 2004.

Theory of a room-temperature silicon quantum dot device as a sensitive electrometer", J. K. Vincent and V. Narayan, H. Pettersson, M. Willander, K. Jeppson, and L. Bengtsson. Journal of Applied Physics, vol 95:1, Jan 1 2004, pp. 323-6.

"Arithmetic circuits combining residue and signed-digit representations", A. Lindström, M. Nordseth, L. Bengtsson and A. Omondi ,  Lecture Notes in  Computer Science (LNCS) vol 2823, pp. 246-257; Springer Verlag, Eighth Asia-Pasific Conference on Computer Systems Architecture, Aiuzu, Japan, 23-26  Sept. 2003.

"A VLSI Array Architecture for Artificial Neural Networks", Lars Bengtsson, Proceedings of the International Conference on Neural Networks and Computational Intelligence (NCI 2003),  May 19-21, 2003, Cancun, Mexico, pp. 50-57.

"Models for Power Consumption Estimation in the DSP-PP Simulator", Do Quang Minh, Lars Bengtsson, and Per Larsson-Edefors, Proceedings of the ISPC'03 International Signal Processing Conference, Dallas, Texas, March 31 - April 3, 2003.

"DSP-PP: A Simulator/Estimator of Power consumption and Performance for Parallel DSP Architectures", Do Quang Minh, Lars Bengtsson, Per Larsson-Ederfors, Proceedings of PDCN'03 Symposium (Parallel and Distributed Computing and Networks), Innsbruck, Austria, Feb 10-13, 2002, pp. 767-772.

"Grid Computing Distribution Using Network Processors", B. Liljeqvist and L. Bengtsson, Proceedings of PDCS'02 (14'th Parallel and Distributed Computing Conference 2002) conference, Nov 4-6, 2002, Cambridge (Boston), USA.

“Novel High-Temperature SET for Electrometer Applications”, J.K.Vincent, V. Narayan, K. Jeppson, L. Bengtsson, H. Pettersson, M. Karlsteen, M. Willander, SSoCC’02: Swedish System-on-Chip Conference 2002, March 18-19, Falkenberg, Sweden, 2002.

"Synchronizing a High-Speed SIMD Processor Array", Stefan Lund and Lars Bengtsson, Proceedings of  DSD'2001: Euromicro Symposium on Digital System, Design, September 4-6, Warzaw, Poland, 2001, pp. 376-381, IEEE Press.

“Propagation Delay Calculations of a Proposed New Low-Power SOI NMOS Transistor”, J.K.Vincent, K. Jeppson, L. Bengtsson, H. Pettersson, M. Karlsteen,  M. Willander, SSoCC’01: Swedish System-on-Chip Conference 2001, March 20-21, Arild, Sweden, 2001.

"Basic Matrix Operations on a DSP Array Architecture", Lars Bengtsson and Stefan Lund, Proceedings of SPC'2000:  International Conference on Signal Processing and Communications, pp. 64-71, Sep 19-22 2000, Marbella, Spain.

"Array Signal Processing with Low Latency", Lars Bengtsson and Stefan Lund, Proceedings of  ICSPAT'99; International Conference on Signal Processing and Technology, Nov 1-4 1999, Orlando, Florida, USA.

"Clock Speed Limitations and Timing in a Radar Signal Processing Architecture", Lars Bengtsson, Proceedings of  SIP'99:  International Conference on Signal and Image Processing, Oct 1999, Nassau, Bahamas.

"A Globally Asynchronous, Locally Synchronous SIMD Processor", Lars Bengtsson and Bertil Svensson, Proceedings of MPCS'98: 3'rd  Bi-Annual  EUROMICRO International Conference on Massively Parallel Computing Systems, Colorado Springs, Colorado, USA, April 2-5, 1998.

"A Scalable SIMD VLSI-architecture with Hierarchical Control", Lars Bengtsson, PhD dissertation, Chalmers University of Technology, 1997.

"A Scalable Massively Parallel SIMD VLSI-architecture with Distributed Control", Lars Bengtsson, Proceedings of  MPCS'96:  2'nd Bi-Annual EUROMICRO Second International Conference on Massively Parallel Computing Systems, Ischia, Italy, May 6-9, 1996, pp. 111-120.

"Brains for Autonomous Robots: Hardware and Surgery Tools", Lars Bengtsson, Bertil Svensson, Per-Arne Wiberg, PerAc'94: Int'l Conf. on
Perception to Action, Lausanne, Switzerland, September 7-9, 1994, pp. 436-439, IEEE Press.

"A High-Performance Embedded Massively Parallel Processing System", Lars Bengtsson, Kenneth Nilsson, Bertil Svensson, Proceedings of MPCS'94: 1'st EUROMICRO International Conference on Massively Parallel Computing Systems, Ischia, Italy, May 1994, pp. 201-206.

"A Processor Array Module for Distributed, Massively Parallel, Embedded Computing", Lars Bengtsson, Kenneth Nilsson, Bertil Svensson, Microprocessing and Microprogramming , Volume 38, Issues 1-5, September 1993, Pages 529-537.

"The REMAP Massively Parallel Computer Platform for Neural Computations, Lars Bengtsson, Arne Linde, Bertil Svensson, Mikael Taveniku,
Anders Åhlander, Proceedings of EURONEURO 93: Third International Conference on Microelectronics for Neural Networks, Edingburgh, Scotland, April 6-8, pp. 47-62,1993.

"Design Issues in a Massively Parallel VLSI-architecture", Lars Bengtsson, DSA 95: 6th Swedish Workshop on Computer System Architecture,
Stockholm, Sweden, June 1-2, 1995.

"A Massively Parallel Architecture for Future Action-Oriented Systems: Possibilities, Solutions and Implementation Aspects", Kenneth Nilsson,
Bertil Svensson, Lars Bengtsson. Proceedings of MCPA'93: International Workshop on Mechatronical Computer Systems for Perception and Action, Halmstad, Sweden, June 1-3, 1993.

"VLSI Implementation of the REMAP-g Massively Parallel, SIMD Array for Embedded Computing", Farzin Akbarzadeh, Lars Bengtsson,
Stefan Lund, Proceedings of MCPA'97: Second International Workshop  on Mechatronical Computer Systems for Perception and Action, Pisa, Italy, Feb 10-12, 1997, pp. 207-211.

" Design and Implementation of the REMAP(3) Software Reconfigurable SIMD Parallel Computer", Lars Bengtsson, Arne Linde, Tomas Nordström,
Bertil Svensson, Mikael Taveniku, Anders Åhlander, DSA-92: the Fourth Swedish Workshop on Computer System Architecture,  Linköping, Sweden, 13-15 January 1992.

Other reports:

"The Effect of Introducing Carrier Sense in an Active RFID Protocol",  Nilsson B., L. Bengtsson, P-A. Wiberg, and B. Svensson, Research Report IDE-0766, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad University, Sweden, 2007.

"0,13 um CMOS Synthesis of Common Arithmetic Uinits", Anders Lindström, Michael Nordseth, Lars Bengtsson, Techn report No 03-11. Dep. of
Computer Engineering, Chalmers Univ of Techn. Göteborg, Aug 2003. See www.ce.chalmers.se/arithdb/

"VHDL Library of Nonstandard Arithmetic Units", Anders Lindström, Michael Nordseth, Lars Bengtsson, Techn report No 03-01. Dep. of Computer
Engineering, Chalmers Univ of Techn. Göteborg, Aug 2003. See www.ce.chalmers.se/arithdb/

"MASS - A low-level Microprogram ASSembler, specification", Lars Bengtsson, Report CCA9103, Centre for Computer Systems Architecture - Halmstad,
Oct.-91 .

"A Control Unit for Bit-Serial SIMD Processor Arrays", Lars Bengtsson, Report CCA9102, Centre for Computer Systems Architecture - Halmstad, Oct.-91 .

"A Processor Module for Bit-Serial SIMD Processor Arrays", Lars Bengtsson, Arne Linde, Mikael Taveniku, Anders Åhlander, Report CCA9401, Centre for
Computer Systems Architecture - Halmstad, Feb.-94.

"Utveckling av Applicationsspecifik Integrerad Krets för Styrändamål" (in swedish), Lars Bengtsson, Report CCA9301 (FOSAM) , Centre for Computer Systems
Architecture - Halmstad, Jan.-93.

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Modified 2011-01-17