library ieee;
use ieee.std_logic_1164.all;
use work.our_types.all;

entity testbench is
end entity testbench;

architecture behavioral of testbench is
  signal clk, reset, ss, lr : std_logic;

  signal out_beh, out_rtl : ... ;
begin
  entity work.stopwatch(behavioral)
      port map (ss, lr, clk, reset, out_beh);

  entity work.stopwatch(structural)
      port map (ss, lr, clk, reset, out_rtl);

  process is
  begin
    ... <= ... ;  -- Assign signals
    wait for ... ;

    ... <= ... ;  -- Assign signals
    wait for ... ;

    ... <= ... ;  -- Assign signals
    wait for ... ;

    -- Good idea to add some sanity checks at various places:
    ASSERT out_beh = ...
    REPORT "behavioral not correct"
    SEVERITY failure;

    ... <= ... ;  -- Assign signals
    wait for ... ;

    ...

  end process;

  -- Ovserver process:
  process (clk) is
  begin
    if rising_edge(clk) then
      if reset = '0' and out_beh /= out_rtl then
        ASSERT false
        REPORT "RTL and behavioral impl. not equal"
        SEVERITY failure;
      end if;
    end if;
  end process;

  -- Clock generator:
  process is
  begin
    clk <= '1';
    wait for 5 us;
    clk <= '0';
    wait for 5 us;
  end process;

end architecture behavioral;