library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

package our_types is
  type display_type is record
    min1 : unsigned(3 downto 0);
    min0 : unsigned(3 downto 0);
    sec1 : unsigned(3 downto 0);
    sec0 : unsigned(3 downto 0);
    hun1 : unsigned(3 downto 0);
    hun0 : unsigned(3 downto 0);
  end record display_type;
end package our_types;

--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.our_types.all;

entity stopwatch is
  port( ss, lr, clk100kHz : in std_logic;
        disp : out display_type := ("0000", "0000", "0000", "0000", "0000", "0000") );
end entity stopwatch;

architecture behavioral of stopwatch is
begin
  sw_beh : process(clk100kHz) is
    variable curr_time : integer := 0;
    ...
  begin
    if rising_edge(clk100kHz) then

      ...

      if ... then
        curr_time := curr_time + 1;
      end if;

      ...
      -- Use / and mod to convert curr_time to digits, and assign to disp.

    end if;
  end process sw_beh;
end architecture behavioral;

--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity counter is
  generic( bits : natural;
           bound : integer );
  port( clk, inc, reset : in std_logic;
        o : out unsigned(bits-1 downto 0);
        carry : out std_logic );
end entity counter;

architecture behavioral of counter is
...
end architecture behavioral;

--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity holder is
  generic( bits: natural );
  port( clk, hold : in std_logic;
        i: in unsigned(bits-1 downto 0);
        o: out unsigned(bits-1 downto 0) );
end entity holder;

architecture behavioral of holder is
  signal old_value: unsigned(bits-1 downto 0) := conv_unsigned(0, bits);
begin
  comb : process(hold, i) is
  begin
    if hold='1' then
      o <= old_value;
    else
      o <= i;
    end if;
  end process comb;

  seq : process(clk) is
  begin
    if rising_edge(clk) then
      if hold='1' then
        old_value <= old_value;
      else
        old_value <= i;
      end if;
    end if;
  end process seq;
end architecture behavioral;

--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity statemachine is
  port( ss_sync, lr_sync, reset, clk : in std_logic;
        running, lapped, countReset : out std_logic );
end entity statemachine;

architecture behavioral of statemachine is
begin
  ...
end architecture behavioral;

--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity synchronous_posedges is
  port( i, clk : in std_logic;
        o : out std_logic := '0' );
end entity synchronous_posedges;

architecture behavioral of synchronous_posedges is
begin
  spe_beh : process(clk) is
    variable last_i : std_logic := '0';
  begin
    if rising_edge(clk) then
      if i = '1' and last_i = '0' then
        o <= '1';
      else
        o <= '0';
      end if;
      last_i := i;
    end if;
  end process spe_beh;
end architecture behavioral;

--------------------------------------------------------------------------------

architecture structural of stopwatch is
  signal ss_sync, lr_sync, running, lapped, countReset, reset : std_logic;
  signal inc_h0, inc_h1, inc_s0, inc_s1, inc_m0, inc_m1: std_logic;
  signal carry_out : std_logic;
  signal drop : unsigned(9 downto 0);
  signal unlapped_disp : display_type;
begin
  sync1 : entity work.synchronous_posedges(behavioral) port map (ss, clk100kHz, ss_sync);
  sync2 : entity work.synchronous_posedges(behavioral) port map (lr, clk100kHz, lr_sync);

  statm : entity work.statemachine(behavioral) port map (ss_sync, lr_sync, reset, clk100kHz,
                                                         running, lapped, countReset);

  count_drop : entity work.counter(behavioral)
               generic map(10, 1000)
               port map (clk100kHz, running, countReset,
                         drop, inc_h0);

  count_h0 : ...

  count_h1 : ...

  count_s0 : ...

  count_s1 : ...

  count_m0 : ...

  count_m1 : ...

  hold_h0 : ...

  hold_h1 : ...

  hold_s0 : ...

  hold_s1 : ...

  hold_m0 : ...

  hold_m1 : ...

end architecture structural;