library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

package our_types is

  type fifo_status is record
                        level                  : natural;
                        empty, half_full, full : std_logic;
                      end record;

end package our_types;

--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.our_types.all;

entity fifo is
  generic(width  : positive := 6;
          length : positive := 5);

  port( clk          : in  std_logic;
        reset        : in  std_logic;

        write_enable : in  std_logic;
        write_data   : in  unsigned(width-1 downto 0);
        write_error  : out std_logic;

        read_enable  : in  std_logic;
        read_data    : out unsigned(width-1 downto 0);
        read_error   : out std_logic;

        status       : out fifo_status);
end entity fifo;

architecture behav of fifo is

  type MemoryType is array (0 to length-1) of
       unsigned(width-1 downto 0);

  type reg_type is record
       memory : MemoryType;
       first : natural;
       . . .
  end record reg_type;

  signal r, rIn : reg_type;

begin

  seq : process(clk,reset) is
  begin
    if reset = '1' then
      r.memory <= (others => (others => '0'));
      r.first  <= 0;
      . . .
    elsif rising_edge(clk) then
      r <= rIn;
    end if;
  end process seq;

  comb : process(r, write_enable, write_data, read_enable) is
  begin
    rIn <= r;

    read_data <= r.memory(r.first);

    . . .

    -- *** Important recommendation:
    --   This process should only read the signals that are listed in the
    --   sensitivity list, and it should only assign to rIn and the output
    --   signals (and perhaps local variables).
  end process comb;

end architecture behav;