Hardware Description and Verification

Mid-course feedback 2010

As part of the standard course evaluation routine, a mid-course feedback meeting was held on 2010-04-26. Attending the meeting:

  • Student representatives: Nikita Frolov and Akshay Vijayshekar.
  • Teacher: Thomas Hallgren
Notes from Akshay:
  • for starters - more VHDL lectures to get a hang of it..
  • ways to test VHDL code - do files to run simulation, test benches.
  • VHDL lectures in pdf format!
  • update Time Edit plz..
Notes from Nikita:
  • people with hardware background really appreciate the course, as it explains more high-level approach to verification than testbenches
  • people with software background find it difficult to catch up on VHDL quickly, provided templates help but not much
  • people with hardware background might not catch up on Haskell/functional programming basics (but ~25% of them had their Haskell-based programming courses at Chalmers)
  • perhaps, more aspects of HDL semantics could be covered (what happens when we compile/synthesize the description, how the AST is translated to the netlist and so on); though, personally, I haven't seen good literature on this subject, there is nothing like "Dragon Book" for hardware description languages
  • perhaps, CS people should have a separate course that focuses on model checking/etc, not on hardware verification
Notes from Thomas
  • More supervised lab sessions? That might be a good idea, but on the other hand, so far this year there has been very few students at the available supervised lab sessions...
  • TimeEdit is schedule is not updated? Hmm, yes. There is currently two schedules: one in TimeEdit and one on the course home page. Neither one is complete. This is confusing and should be avoided in the future. Preferably, all information should be put in the TimeEdit schedule.
  • Most of the students come from two different Master's programs:

    This means that they have rather different background. Students from [2] have little experience with VHDL, VHDL tools and the circuit design workflow. Apparently some students quit early on this year because they didn't think they knew enough about this. On the other hand, for students from [1], the VHDL circuits descriptions we work with in this course are very simple.

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