Computer Engineering Division
Computer Science Engineering Department
Chalmers University of Technology
412 96 Gothenburg
sourdis at institution dot se
+46 31 772 1744 office
+46 31 772 3663 fax
Rännvägen 6, 4th floor, E/D/IT (D&IT), room no. 4110
- Architectures and Design of Computing systems
- Network Processing
- Network Security, Intrusion Detection, Content Inspection, Pattern Matching
- IP-Lookup, Packet Classification
- Reconfigurable Computing
- Fault-Tolerant Computing
- Interconnection Networks and Networks-on-Chip
- Multicore Architectures
- ECOSCALE: Energy-efficient Heterogeneous COmputing at exaSCALE, FET-HPC, Horizon 2020, Oct. 2015-Sept. 2018.
- SHARCS: Secure HW-SW Architectures for Robust Computing Systems, Horizon 2020, Jan. 2015- Dec. 2017.
- COSSIM: Comprehensible, Ultra-Fast, Security-Aware CPS Simulator, Horizon 2020, Feb. 2015- Jan. 2018.
- EUROSERVER: Green Computing Node for European micro-servers, Horizon 2020, Sept. 2013- Jan. 2017, (PI: Per Stenstrom).
- ACE: Approximate Algorithms and Computing Systems, VR, 2015-2018, (PI: Per Stenstrom).
- EMC2: Embedded Multi-Core Systems for Mixed Criticality Applications in Dynamic and Changeable Real-Time Environment, Artemis JI, Apr. 2014- Mar. 2017.
- DeSyRe: on-Demand System Reliability, European FP7 project, 2011-2015
- STW Valorisation grant (Dutch) for the Range Trie invention 2010
- HiPEAC coordination of the Reconfigurable Computing research cluster 2007-2010, (PI: G. Gaydadjiev).
- SARC: Scalable Computer Architecture, FP6 EU project (IP FET), 2006-2010 (PI: G. Gaydadjiev).
- EASY: Energy-aware System-on-Chip design of the HIPERLAN/2 standard, FP5 EU project, 2003-2004 (PI: D. Pnevmatikatos).
- Pro3: The Protocol Processor Project, FP5 EU project, 2000-2002 (PI: D. Pnevmatikatos).
- Award for co-authoring one of the most significant FPL papers (in the 25 years history of the conference), that most strongly influenced theory and practice in the field, 2015. For the paper: I. Sourdis and D.N. Pnevmatikatos, "Fast, Large-Scale String Match for a 10Gbps FPGA-based Network Intrusion Detection System", 13th Int. Conf. on Field Programmable Logic and Applications (FPL), pp. 880Ð889, 2003.
- Second price on the IEEE FPT Design Competition, 2009.
- I coordinated the FP7 colaborative research project DeSyRe: on-Demand System Reliability
- I was a member of the Management Committee of the ICT COST Action IC1103 on Manufacturable and Dependable Multicore Architectures at Nanoscale
- Member of the the European Network of Excellence (NoE) on High-Perfomance and Embedded Architecture and Compilation (HiPEAC)
- Member of the IEEE and the ACM